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51. 发明授权

US07818490B2 Partial block data programming and reading operations in a non-volatile memory 有权
公开(公告)号：US07818490B2
公开(公告)日：2010-10-19
申请号：US11250238
申请日：2005-10-13
申请人： Kevin M. Conley
发明人： Kevin M. Conley
IPC分类号： G06F9/24
CPC分类号： G11C16/102 , G06F12/0246 , G06F2212/1016 , G06F2212/1032 , G06F2212/7202 , G06F2212/7208 , G06F2212/7209 , G11C16/105 , G11C2216/16
摘要： Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

52. 发明授权

US07762849B2 Expandable and collapsible peripheral device 有权
标题翻译：可扩展和可折叠的外围设备
公开(公告)号：US07762849B2
公开(公告)日：2010-07-27
申请号：US12103533
申请日：2008-04-15
申请人： Jonathan Hubert , Jason P. Hanlon , Kevin M. Conley
发明人： Jonathan Hubert , Jason P. Hanlon , Kevin M. Conley
IPC分类号： H01R24/00
CPC分类号： G06K19/077 , G06K19/07732
摘要： An expandable and collapsible peripheral device is disclosed, along with methods of manufacturing same. When in an expanded state, the peripheral device may have a length which conforms to the ExpressCard standard, and when in a collapsed state, the peripheral device may have a form factor approximating that of a CompactFlash card. Peripheral devices of the present invention may operate according to standards other than the ExpressCard standard, and may have sizes in the expanded and collapsed positions unrelated to ExpressCards and/or CompactFlash cards.
摘要翻译：公开了可扩展和可折叠的外围设备及其制造方法。当处于扩展状态时，外围设备可以具有符合ExpressCard标准的长度，并且当处于折叠状态时，外围设备可以具有接近CompactFlash卡的形状因子。本发明的外围设备可以根据ExpressCard标准以外的标准进行操作，并且可以具有与ExpressCard和/或CompactFlash卡无关的扩展位置和折叠位置的尺寸。

53. 发明申请

US20090313432A1 Memory device storing a plurality of digital media files and playlists 审中-公开
标题翻译：存储设备存储多个数字媒体文件和播放列表
公开(公告)号：US20090313432A1
公开(公告)日：2009-12-17
申请号：US12157846
申请日：2008-06-13
申请人： Richard C. Spence , Kevin M. Conley
发明人： Richard C. Spence , Kevin M. Conley
IPC分类号： G06F12/00
CPC分类号： G11B27/105 , G06F16/4387 , G11B2220/61 , G11B2220/65
摘要： A memory device storing a plurality of digital media files and playlists is disclosed. The memory device comprises a connector configured to be connected with a digital media player and a memory in communication with the connector. In one embodiment, each playlist is created by a curator. In another embodiments at least one playlist specifies at least one digital media file that is not specified by another playlist in the plurality of playlists. In yet another embodiment, a first plurality of playlists are associated with a first channel, and a second plurality of playlists are associated with a second channel, wherein each playlist specifies a predetermined play order of at least some of the plurality of digital media files.
摘要翻译：公开了存储多个数字媒体文件和播放列表的存储装置。存储装置包括被配置为与数字媒体播放器连接的连接器和与连接器通信的存储器。在一个实施例中，每个播放列表由策展人创建。在另一个实施例中，至少一个播放列表指定多个播放列表中未由另一个播放列表指定的至少一个数字媒体文件。在另一个实施例中，第一多个播放列表与第一信道相关联，并且第二多个播放列表与第二信道相关联，其中每个播放列表指定多个数字媒体文件中的至少一些的预定播放顺序。

54. 发明授权

US07631138B2 Adaptive mode switching of flash memory address mapping based on host usage characteristics 有权
标题翻译：基于主机使用特性的闪存地址映射的自适应模式切换
公开(公告)号：US07631138B2
公开(公告)日：2009-12-08
申请号：US10750190
申请日：2003-12-30
申请人： Carlos J. Gonzalez , Mark Sompel , Kevin M. Conley
发明人： Carlos J. Gonzalez , Mark Sompel , Kevin M. Conley
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7202 , G06F2212/7208
摘要： In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.
摘要翻译：在诸如闪存EEPROM系统的非易失性存储器系统中，响应于主机编程和控制器数据合并模式，控制器将数据扇区映射到存储器的块和元区块的方式切换，以便提高性能和减少磨损。数据被编程到具有不同程度的并行性的存储器中。

55. 发明申请

US20080191032A1 EXPANDABLE AND COLLAPSIBLE PERIPHERAL DEVICE 有权
标题翻译：可扩展和可拆卸的外围设备
公开(公告)号：US20080191032A1
公开(公告)日：2008-08-14
申请号：US12103533
申请日：2008-04-15
申请人： Jonathan Hubert , Jason P. Hanlon , Kevin M. Conley
发明人： Jonathan Hubert , Jason P. Hanlon , Kevin M. Conley
IPC分类号： G06K19/067
CPC分类号： G06K19/077 , G06K19/07732
摘要： An expandable and collapsible peripheral device is disclosed, along with methods of manufacturing same. When in an expanded state, the peripheral device may have a length which conforms to the ExpressCard standard, and when in a collapsed state, the peripheral device may have a form factor approximating that of a CompactFlash card. Peripheral devices of the present invention may operate according to standards other than the ExpressCard standard, and may have sizes in the expanded and collapsed positions unrelated to ExpressCards and/or CompactFlash cards.
摘要翻译：公开了可扩展和可折叠的外围设备及其制造方法。当处于扩展状态时，外围设备可以具有符合ExpressCard标准的长度，并且当处于折叠状态时，外围设备可以具有接近CompactFlash卡的形状因子。本发明的外围设备可以根据ExpressCard标准以外的标准进行操作，并且可以具有与ExpressCard和/或CompactFlash卡无关的扩展位置和折叠位置的尺寸。

56. 发明授权

US07409473B2 Off-chip data relocation 有权
标题翻译：片外数据迁移
公开(公告)号：US07409473B2
公开(公告)日：2008-08-05
申请号：US11022462
申请日：2004-12-21
申请人： Kevin M. Conley , Peter John Smith
发明人： Kevin M. Conley , Peter John Smith
IPC分类号： G06F13/14
CPC分类号： G11C16/10 , G11C16/26
摘要： The on-chip copy process is extended so that the data may be copied between two blocks that may be on different chips, different planes on the same chip, or the same plane of the same chip. More specifically, the methods described here provide a single data copying mechanism that allows data to be copied between any two locations in a memory system. An exemplary embodiment uses an EDO-type timing. According to another aspect, selected portions of the relocated data, such as chosen words in a transferred page, can be updated in the controller on the fly. In addition to transferring a data set directly from a read buffer of a source array to a write buffer of a destination array, the data set can concurrently be copied, if desired, into the controller where an error detection and correction operation can be performed on it.
摘要翻译：片上复制处理被扩展，使得可以在可以在不同芯片上的两个块之间，同一芯片上的不同平面或同一芯片的同一平面上复制数据。更具体地说，这里描述的方法提供了允许在存储器系统中的任何两个位置之间复制数据的单个数据复制机制。示例性实施例使用EDO型定时。根据另一方面，可以在控制器中即时更新重新定位的数据的所选部分，例如传送页面中的所选择的单词。除了将数据集直接从源阵列的读缓冲器传送到目的地阵列的写缓冲器之外，如果需要，数据组可以同时复制到控制器中，其中可以执行错误检测和校正操作它。

57. 发明授权

US07408834B2 Flash controller cache architecture 有权
标题翻译：闪存控制器缓存架构
公开(公告)号：US07408834B2
公开(公告)日：2008-08-05
申请号：US11671394
申请日：2007-02-05
申请人： Kevin M. Conley , Reuven Elhamias
发明人： Kevin M. Conley , Reuven Elhamias
IPC分类号： G11C8/00
CPC分类号： G06F12/0862 , G06F12/0804 , G06F12/0866 , G06F2212/2022 , G06F2212/214 , G06F2212/2146 , G06F2212/282 , G06F2212/502
摘要： A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write back and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.
摘要翻译：介于非易失性存储器和主机之间的缓冲器高速缓存可被划分成可以不同策略操作的段。缓存策略包括直写，回写和预读。直写和回写策略可能会提高速度。预读高速缓存允许在缓冲器高速缓存和非易失性存储器之间更有效地使用总线。会话命令允许通过保证防止功率损耗来将数据保存在易失性存储器中。

58. 发明申请

US20080092026A1 Methods of Soft-Input Soft-Output Decoding for Nonvolatile Memory 有权
标题翻译：用于非易失性存储器的软输入软输出解码方法
公开(公告)号：US20080092026A1
公开(公告)日：2008-04-17
申请号：US11536286
申请日：2006-09-28
申请人： Yigal Brandman , Kevin M. Conley
发明人： Yigal Brandman , Kevin M. Conley
IPC分类号： H03M13/03
CPC分类号： G06F11/1072 , H03M13/1102 , H03M13/2906 , H03M13/2963 , H03M13/45
摘要： In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.
摘要翻译：在非易失性存储器系统中，从存储器阵列中读取数据并用于获得似然值，然后提供给软输入软输出解码器。软输入软输出解码器从输入似然值和根据编码方案先前添加的奇偶校验数据计算输出似然值。

59. 发明申请

US20080082897A1 Soft-Input Soft-Output Decoder for Nonvolatile Memory 有权
标题翻译：用于非易失性存储器的软输入软输出解码器
公开(公告)号：US20080082897A1
公开(公告)日：2008-04-03
申请号：US11536327
申请日：2006-09-28
申请人： Yigal Brandman , Kevin M. Conley
发明人： Yigal Brandman , Kevin M. Conley
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G06F11/1068 , G11C16/0483 , G11C2029/0411
摘要： In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.
摘要翻译：在非易失性存储器系统中，从存储器阵列中读取数据并用于获得似然值，然后提供给软输入软输出解码器。软输入软输出解码器从输入似然值和根据编码方案先前添加的奇偶校验数据计算输出似然值。

60. 发明申请

US20070088940A1 Initialization of flash storage via an embedded controller 有权
标题翻译：通过嵌入式控制器初始化闪存
公开(公告)号：US20070088940A1
公开(公告)日：2007-04-19
申请号：US11250094
申请日：2005-10-13
申请人： Kevin M. Conley
发明人： Kevin M. Conley
IPC分类号： G06F15/177
CPC分类号： G11C16/20 , G06F9/445
摘要： A digital system including flash memory, coupled to a system-on-a-chip within which a flash memory subsystem controller is embedded, is disclosed. The system-on-a-chip includes support for a standard external interface, such as a Universal Serial Bus (USB) or IEEE 1394 interface, to which a host system such as flash memory test equipment can connect. Initialization of the flash memory is effected by opening a communications channel between the host system and the embedded flash memory subsystem controller. The host system can then effect initialization of the flash memory subsystem, including formatting of the flash memory arrays, loading application programs, and the like, over the communications channel.
摘要翻译：公开了一种包括快闪存储器的数字系统，其耦合到其中嵌入有闪存子系统控制器的片上系统。片上系统包括对标准外部接口（如通用串行总线（USB）或IEEE 1394接口）的支持，诸如闪存测试设备的主机系统可以连接到该接口。通过打开主机系统和嵌入式闪存子系统控制器之间的通信通道来实现闪存的初始化。然后，主机系统可以通过通信信道来实现闪存子系统的初始化，包括闪存阵列的格式化，加载应用程序等。

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