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    • 55. 发明申请
    • MIS-TRANSISTOR-BASED NONVOLATILE MEMORY FOR MULTILEVEL DATA STORAGE
    • 基于MIS-TRANSISTOR的非易失性存储器,用于多种数据存储
    • US20090310428A1
    • 2009-12-17
    • US12139550
    • 2008-06-16
    • Tadahiko HoriuchiKenji Noda
    • Tadahiko HoriuchiKenji Noda
    • G11C7/00
    • G11C11/5671G11C2211/5642G11C2211/5647
    • A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.
    • 存储器电路包括具有第一节点和第二节点的锁存器,用于存储数据,使得第一节点的逻辑电平为第二节点的逻辑电平的倒数,具有门节点的MIS晶体管,第一源极/ 漏极节点和第二源极/漏极节点,耦合到锁存器的第一节点的第一源极/漏极节点以及控制电路,被配置为控制MIS晶体管的栅极节点和第二源极/漏极节点向上 响应于存储在锁存器中的数据,在第一操作中MIS晶体管的阈值电压的持续变化,并且响应于存储在锁存器中的数据,在第二操作中使阈值电压下降。
    • 56. 发明授权
    • MIS-transistor-based nonvolatile memory
    • 基于MIS晶体管的非易失性存储器
    • US07630247B2
    • 2009-12-08
    • US12036938
    • 2008-02-25
    • Kenji Noda
    • Kenji Noda
    • G11C16/04
    • G11C14/00G11C14/0063
    • A nonvolatile semiconductor memory device includes a latch circuit including a first inverter and a second inverter cross-coupled to each other, a source node of a MIS transistor of the first inverter and a source node of a MIS transistor of the second inverter being both coupled to a plate line, and a control circuit configured to apply a first potential to the plate line in a store mode to cause a change in threshold voltage to one of the MIS transistors, and configured to apply a second potential to the plate line in a power-on mode to cause the latch circuit to latch data responsive to the change in threshold voltage generated in the store mode, such that the data latched by the latch circuit in the power-on mode is automatically output to outside the nonvolatile semiconductor memory device upon power-on thereof.
    • 一种非易失性半导体存储器件,包括:锁存电路,包括第一反相器和彼此交叉耦合的第二反相器,第一反相器的MIS晶体管的源极节点和第二反相器的MIS晶体管的源极节点都耦合 以及控制电路,其被配置为在存储模式下向所述板线施加第一电位,以引起对所述MIS晶体管之一的阈值电压的改变,并且被配置为向所述板线施加第二电位 电源接通模式,以使得锁存电路根据在存储模式下产生的阈值电压的变化来锁存数据,使得由电源接通模式中的锁存电路锁存的数据自动输出到非易失性半导体存储器件外部 上电时。
    • 57. 发明授权
    • Nonvolatile memory utilizing hot-carrier effect with data reversal function
    • 使用具有数据反转功能的热载波效应的非易失性存储器
    • US07483290B2
    • 2009-01-27
    • US11701958
    • 2007-02-02
    • Takashi KikuchiKenji Noda
    • Takashi KikuchiKenji Noda
    • G11C11/00
    • G11C14/00G11C14/0063
    • A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit, and memory units, each of the memory units including a latch having a first node and a second node, a plate line, a first MIS transistor having one of source/drain nodes coupled to the first node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to a word line, and a second MIS transistor having one of source/drain nodes coupled to the second node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to the word line, wherein the control circuit is configured to invert the data latched in the latch by reading the data from the latch, causing the inverting circuit to invert the read data, and writing the inverted data to the latch.
    • 非易失性半导体存储器件包括控制电路,反相电路和存储器单元,每个存储器单元包括具有第一节点和第二节点的锁存器,板线,具有源/漏节点之一的第一MIS晶体管 耦合到锁存器的第一节点,耦合到板线的源极/漏极节点中的另一个以及耦合到字线的栅极节点以及耦合到第二节点的源极/漏极节点之一的第二MIS晶体管 耦合到板线的源/漏节点中的另一个和耦合到字线的栅极节点,其中控制电路被配置为通过从锁存器读取数据来反转锁存在锁存器中的数据, 使反相电路反转读取的数据,并将反相数据写入锁存器。
    • 59. 发明申请
    • HOT-CARRIER-BASED NONVOLATILE MEMORY UTILIZING DIFFERING TRANSISTOR STRUCTURES
    • 基于热载体的非易失性存储器利用不同的晶体管结构
    • US20080062745A1
    • 2008-03-13
    • US11518066
    • 2006-09-08
    • Kenji Noda
    • Kenji Noda
    • G11C16/04G11C11/00G11C11/34G11C7/10
    • G11C11/412G11C16/10H01L29/66825H01L29/7881
    • A memory circuit includes a latch having a first node and a second node, a first MIS transistor operable to couple between the first node and a predetermined node, a second MIS transistor operable to couple between the second node and the predetermined node, and a control circuit configured to subject one of the first MIS transistor and the second MIS transistor to bias conditions that cause a lingering change in transistor characteristics thereof, wherein the MIS transistors of the latch have a lightly-doped-drain structure that includes first diffusion regions having a first impurity concentration and second diffusion regions having a second impurity concentration smaller than the first impurity concentration, and each of the first MIS transistor and the second MIS transistor has a doped diffusion region closest to a conduction channel with an impurity concentration different from the second impurity concentration.
    • 存储器电路包括具有第一节点和第二节点的锁存器,可操作以在第一节点和预定节点之间耦合的第一MIS晶体管,可操作以在第二节点和预定节点之间耦合的第二MIS晶体管,以及控制器 电路,被配置为使所述第一MIS晶体管和所述第二MIS晶体管中的一个偏置导致其晶体管特性的延迟变化的条件,其中所述锁存器的所述MIS晶体管具有轻掺杂漏极结构,所述轻掺杂漏极结构包括具有 第一杂质浓度和第二杂质浓度小于第一杂质浓度的第二扩散区,并且第一MIS晶体管和第二MIS晶体管中的每一个具有最靠近导电沟道的掺杂扩散区,杂质浓度不同于第二杂质浓度 浓度。
    • 60. 发明授权
    • Hot-carrier-based nonvolatile memory utilizing differing transistor structures
    • 采用不同晶体管结构的基于热载波的非易失性存储器
    • US07342821B1
    • 2008-03-11
    • US11518066
    • 2006-09-08
    • Kenji Noda
    • Kenji Noda
    • G11C11/00
    • G11C11/412G11C16/10H01L29/66825H01L29/7881
    • A memory circuit includes a latch having a first node and a second node, a first MIS transistor operable to couple between the first node and a predetermined node, a second MIS transistor operable to couple between the second node and the predetermined node, and a control circuit configured to subject one of the first MIS transistor and the second MIS transistor to bias conditions that cause a lingering change in transistor characteristics thereof, wherein the MIS transistors of the latch have a lightly-doped-drain structure that includes first diffusion regions having a first impurity concentration and second diffusion regions having a second impurity concentration smaller than the first impurity concentration, and each of the first MIS transistor and the second MIS transistor has a doped diffusion region closest to a conduction channel with an impurity concentration different from the second impurity concentration.
    • 存储器电路包括具有第一节点和第二节点的锁存器,可操作以在第一节点和预定节点之间耦合的第一MIS晶体管,可操作以在第二节点和预定节点之间耦合的第二MIS晶体管,以及控制器 电路,被配置为使所述第一MIS晶体管和所述第二MIS晶体管中的一个偏置导致其晶体管特性的延迟变化的条件,其中所述锁存器的所述MIS晶体管具有轻掺杂漏极结构,所述轻掺杂漏极结构包括具有 第一杂质浓度和第二杂质浓度小于第一杂质浓度的第二扩散区,并且第一MIS晶体管和第二MIS晶体管中的每一个具有最靠近导电沟道的掺杂扩散区,杂质浓度不同于第二杂质浓度 浓度。