专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08501508B2 Method of forming quantum well mosfet channels having uni-axial strains caused by metal source/drains 有权
标题翻译：形成具有由金属源/排水管引起的单轴应变的量子阱mosfet通道的方法
公开(公告)号：US08501508B2
公开(公告)日：2013-08-06
申请号：US13479121
申请日：2012-05-23
申请人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L21/00
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
摘要翻译：所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变顶部阻挡层和量子阱的底部缓冲层。

52. 发明授权

US08115235B2 Modulation-doped halo in quantum well field-effect transistors, apparatus made therewith, and methods of using same 有权
标题翻译：量子阱场效应晶体管中的调制掺杂晕，其制造的装置及其使用方法
公开(公告)号：US08115235B2
公开(公告)日：2012-02-14
申请号：US12378828
申请日：2009-02-20
申请人： Ravi Pillarisetty , Titash Rakshit , Mantu Hudait , Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung
发明人： Ravi Pillarisetty , Titash Rakshit , Mantu Hudait , Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung
IPC分类号： H01L31/06
CPC分类号： H01L29/122 , B82Y10/00 , H01L29/045 , H01L29/205 , H01L29/207 , H01L29/4236 , H01L29/51 , H01L29/66462 , H01L29/7785
摘要： A quantum well (QW) layer is provided in a semiconductive device. The QW layer is provided with a beryllium-doped halo layer in a barrier structure below the QW layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.
摘要翻译：在半导体器件中提供量子阱（QW）层。 QW层在QW层下面的阻挡结构中设置有铍掺杂卤素层。半导体器件包括分别在QW层下方和上方的InGaAs底部和顶部势垒层。半导体器件还包括位于栅极凹槽中的InP间隔物第一层上的高k栅介质层。形成QW层的方法包括使用切断的半导体衬底。

53. 发明申请

US20100213441A1 Modulation-doped halos in quantum well field-effect transistors, apparatus made therewith, and methods of using same 有权
标题翻译：量子阱场效应晶体管中的调制掺杂光晕，其制造的装置及其使用方法
公开(公告)号：US20100213441A1
公开(公告)日：2010-08-26
申请号：US12378828
申请日：2009-02-20
申请人： Ravi Pillarisetty , Titash Rakshit , Mantu Hudait , Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung
发明人： Ravi Pillarisetty , Titash Rakshit , Mantu Hudait , Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung
IPC分类号： H01L29/80 , H01L21/3205
CPC分类号： H01L29/122 , B82Y10/00 , H01L29/045 , H01L29/205 , H01L29/207 , H01L29/4236 , H01L29/51 , H01L29/66462 , H01L29/7785
摘要： A quantum well (QW) layer is provided in a semiconductive device. The QW layer is provided with a beryllium-doped halo layer in a barrier structure below the QW layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.
摘要翻译：在半导体器件中提供量子阱（QW）层。 QW层在QW层下面的阻挡结构中设置有铍掺杂卤素层。半导体器件包括分别在QW层下方和上方的InGaAs底部和顶部势垒层。半导体器件还包括位于栅极凹槽中的InP间隔物第一层上的高k栅介质层。形成QW层的方法包括使用切断的半导体衬底。

54. 发明申请

US20100193771A1 QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS 有权
标题翻译：具有由金属源/排水源引起的不均匀应变的QUANTUM WELL MOSFET通道，以及合适的反应源/漏极
公开(公告)号：US20100193771A1
公开(公告)日：2010-08-05
申请号：US12756989
申请日：2010-04-08
申请人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L29/772
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
摘要翻译：所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变顶部阻挡层和量子阱的底部缓冲层。

55. 发明申请

US20100163847A1 QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS 失效
公开(公告)号：US20100163847A1
公开(公告)日：2010-07-01
申请号：US12347268
申请日：2008-12-31
申请人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L29/12 , H01L21/336 , H01L21/18 , H01L21/203
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

56. 发明授权

US07700975B2 Schottky barrier metal-germanium contact in metal-germanium-metal photodetectors 失效
标题翻译：金属锗金属光电探测器中的肖特基势垒金 - 锗接触
公开(公告)号：US07700975B2
公开(公告)日：2010-04-20
申请号：US11394817
申请日：2006-03-31
申请人： Titash Rakshit , Miriam Reshotko
发明人： Titash Rakshit , Miriam Reshotko
IPC分类号： H01L29/739 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/80 , H01L31/112 , H01L31/00 , H01L27/095 , H01L29/47 , H01L29/812 , H01L31/07
CPC分类号： H01L31/1085 , H01L31/022408
摘要： Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) layer deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. In one embodiment, the semiconductor layer is an intrinsic semiconductor layer. In one embodiment, the thickness of the delta doped layer is less than 100 nanometers. In one embodiment, the delta doped layer has a dopant concentration of at least 1×1018 cm−3. A delta doped layer is formed on portions of a semiconductor layer over a substrate. Metal contacts are formed on the delta doped layer. A buffer layer may be formed between the substrate and the semiconductor layer. In one embodiment, the substrate includes silicon, and the semiconductor layer includes germanium.
摘要翻译：描述了金属 - 半导体 - 金属（“MSM”）光电探测器及其制造方法。 MSM光电检测器包括沉积在金属触点和半导体层之间的界面处的薄重掺杂（“δ掺杂”）层，以减少MSM光电探测器的暗电流。在一个实施例中，半导体层是本征半导体层。在一个实施例中，Δ掺杂层的厚度小于100纳米。在一个实施例中，δ掺杂层具有至少1×10 18 cm -3的掺杂剂浓度。在衬底上的半导体层的部分上形成δ掺杂层。在δ掺杂层上形成金属接触。可以在衬底和半导体层之间形成缓冲层。在一个实施例中，衬底包括硅，并且半导体层包括锗。

57. 发明授权

US07642603B2 Semiconductor device with reduced fringe capacitance 有权
标题翻译：具有降低的边缘电容的半导体器件
公开(公告)号：US07642603B2
公开(公告)日：2010-01-05
申请号：US11823892
申请日：2007-06-29
申请人： Suman Datta , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
发明人： Suman Datta , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.
摘要翻译：在本发明的一个实施例中，非平面晶体管包括栅电极和多个散热片。沟槽接触件连接到鳍片。接触底部形成在衬底之上并且不直接接触衬底。触点底部高于门顶。

58. 发明申请

US20090315114A1 STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS 有权
标题翻译：使用复合栅填充材料的触发器件中的应力
公开(公告)号：US20090315114A1
公开(公告)日：2009-12-24
申请号：US12144469
申请日：2008-06-23
申请人： Titash Rakshit , Martin Giles , Ravi Pillarisetty , Jack T. Kavalieros
发明人： Titash Rakshit , Martin Giles , Ravi Pillarisetty , Jack T. Kavalieros
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L29/7845 , H01L21/8234 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/495 , H01L29/66795 , H01L29/7831 , H01L29/785
摘要： Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.
摘要翻译：实施例涉及具有栅极金属填充物的改进的三栅极器件，在三栅极晶体管的至少一部分上提供压缩或拉伸应力，由此增加载流子迁移率和工作频率。实施例还考虑了使用改进的三栅极器件的方法。

59. 发明申请

US20090230478A1 APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMACE 有权
标题翻译：改进多门装置性能的装置和方法
公开(公告)号：US20090230478A1
公开(公告)日：2009-09-17
申请号：US12049078
申请日：2008-03-14
申请人： Ravi Pillarisetty , Brian Doyle , Titash Rakshit , Jack Kavalieros
发明人： Ravi Pillarisetty , Brian Doyle , Titash Rakshit , Jack Kavalieros
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L29/7855 , H01L29/66545 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.
摘要翻译：本文通常描述用于提高多栅极器件性能的装置和方法的实施例。可以描述和要求保护其他实施例。

60. 发明申请

US20080001181A1 Complementarily doped metal-semiconductor interfaces to reduce dark current in MSM photodetectors 审中-公开
标题翻译：互补掺杂的金属 - 半导体界面，以减少MSM光电探测器中的暗电流
公开(公告)号：US20080001181A1
公开(公告)日：2008-01-03
申请号：US11477722
申请日：2006-06-28
申请人： Titash Rakshit , Miriam Reshotko
发明人： Titash Rakshit , Miriam Reshotko
IPC分类号： H01L27/148
CPC分类号： H01L31/1085 , H01L31/18
摘要： Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) regions deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. Band engineering at the metal-semiconductor interfaces using complementarily delta doped semiconductor regions to fix two different interface workfunctions. Delta doping the grounded contact interface with p+ and the reverse biased interface with n+ enhances the Schottky barrier faced by both electrons and holes at the point of injection from source contact into the channel and at the point of collection from the channel into the drain contact.
摘要翻译：描述了金属 - 半导体 - 金属（“MSM”）光电探测器及其制造方法。 MSM光电检测器包括沉积在金属触点和半导体层之间的界面处的薄重掺杂（“δ掺杂”）区域，以减少MSM光电探测器的暗电流。使用互补的δ掺杂半导体区域在金属 - 半导体界面处的带工程化以固定两个不同的界面工作功能。使用p +掺杂接地接触界面的增益和具有n +的反向偏置界面的增强了在源极接触到通道中以及从通道到漏极接触点的注入点处的电子和空穴所面临的肖特基势垒的肖特基势垒。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式