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51. 发明授权

US07412587B2 Parallel operation processor utilizing SIMD data transfers 有权
标题翻译：并行运算处理器利用SIMD数据传输
公开(公告)号：US07412587B2
公开(公告)日：2008-08-12
申请号：US11054049
申请日：2005-02-09
申请人： Takeshi Tanaka , Hideshi Nishida , Masashi Hoshino , Takeshi Furuta
发明人： Takeshi Tanaka , Hideshi Nishida , Masashi Hoshino , Takeshi Furuta
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30181 , G06F9/3824 , G06F9/3826 , G06F9/3828 , G06F9/3887 , G06F15/8015
摘要： A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred; a transfer unit operable to perform a data transfer from the processing element indicated by the transfer pattern value; and an update unit operable to update the transfer pattern value stored in the transfer pattern storage unit, in accordance with a result of decoding a latest instruction by the decoder.
摘要翻译：具有多个处理元件的处理器和可解码指令的解码器。多个处理元件中的每一个包括：传送图案存储单元，用于存储指示从其传送数据的处理元件的传送图案值; 传送单元，其可操作以从由所述传送图案值指示的处理单元执行数据传送; 以及更新单元，用于根据由解码器解码最新指令的结果来更新存储在传送模式存储单元中的传送模式值。

52. 发明申请

US20120036336A1 INFORMATION PROCESSOR 有权
标题翻译：信息处理器
公开(公告)号：US20120036336A1
公开(公告)日：2012-02-09
申请号：US13265172
申请日：2010-04-15
申请人： Hideshi Nishida
发明人： Hideshi Nishida
IPC分类号： G06F9/38 , G06F13/14
CPC分类号： G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3887 , G06F9/3889
摘要： The present invention provides an information processing apparatus and an integrated circuit which realize parallel execution of different processing systems, and which do not require the provision of a dedicated memory storing instructions for common processing The information processing apparatus comprises: a plurality of processor elements; an instruction memory storing a first program and a second program; and an arbiter interposed between the processor elements and the instruction memory, the arbiter receiving, from each of the processor elements, a request for an instruction, from among instructions included in the first program and the second program, and controlling access to the instruction memory by the processor elements, wherein the arbiter arbitrates requests made by the processor elements when the requests are (i) simultaneous requests for different instructions included in one of the first program and the second program or (ii) simultaneous requests for an instruction included in the first program and an instruction included in the second program, and when two or more of the processor elements simultaneously request a same instruction included in one of the first program and the second program, the arbiter, when judging that the instruction memory is available to the two or more processor elements, outputs the same instruction to the two or more processor elements.
摘要翻译：本发明提供一种信息处理装置和集成电路，其实现不同处理系统的并行执行，并且不需要提供存储用于公共处理的指令的专用存储器。信息处理装置包括：多个处理器元件; 存储第一程序和第二程序的指令存储器; 以及插入在所述处理器元件和所述指令存储器之间的仲裁器，所述仲裁器从每个所述处理器元件从所述第一程序和所述第二程序中包括的指令中接收对指令的请求，并且控制对所述指令存储器的访问所述处理器元件，其中所述仲裁器在所述请求是（i）对包括在所述第一程序和所述第二程序之一中的不同指令的同时请求时仲裁由所述处理器单元作出的请求，或者（ii）同时请求包括在所述第一程序和所述第二程序中的指令第一程序和包括在第二程序中的指令，并且当两个或更多个处理器单元同时请求包括在第一程序和第二程序之一中的相同指令时，仲裁器在判断指令存储器可用于两个或多个处理器元件向两个或多个处理器元件输出相同的指令。

53. 发明授权

US08086830B2 Arithmetic processing apparatus 有权
标题翻译：算术处理装置
公开(公告)号：US08086830B2
公开(公告)日：2011-12-27
申请号：US11720899
申请日：2005-08-24
申请人： Takeshi Furuta , Hideshi Nishida , Takeshi Tanaka
发明人： Takeshi Furuta , Hideshi Nishida , Takeshi Tanaka
IPC分类号： G06F15/80 , G06F9/302 , G06F9/305
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30058 , G06F9/30072 , G06F9/3885
摘要： An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic processing apparatus, which processes multiple data in parallel based on single instruction, includes: processing elements capable of performing a common arithmetic operation based on the evaluation result of the instruction stored in the instruction register; and a condition flag arithmetic operation unit capable of performing one of the logical operation and the comparison operation on the condition flag retained in each processing element, transferring the operation result to each processing element, and updating the condition flag based on the operation result.
摘要翻译：提供一种算术处理装置，其能够以尽可能少的步长进行用于生成通常使用在算术运算单元上生成的条件标志共同参照的条件标志的算术运算。基于单个指令并行处理多个数据的算术处理装置包括：能够基于存储在指令寄存器中的指令的评估结果执行公共算术运算的处理单元; 以及条件标志算术运算单元，其能够对保留在每个处理单元中的条件标志执行逻辑运算和比较运算中的一个，将运算结果传送给各处理单元，并根据运算结果更新条件标志。

54. 发明申请

US20110216247A1 SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, INTEGRATED CIRCUIT FOR SIGNAL PROCESSING, AND TELEVISION RECEIVER 审中-公开
标题翻译：信号处理装置，信号处理方法，用于信号处理的集成电路和电视接收机
公开(公告)号：US20110216247A1
公开(公告)日：2011-09-08
申请号：US12671542
申请日：2009-06-03
申请人： Hideshi Nishida
发明人： Hideshi Nishida
IPC分类号： H04N5/44 , H03K19/173
CPC分类号： H03K19/17776 , H03K19/17756 , H04N5/14 , H04N5/4401 , H04N21/426 , H04N21/4432
摘要： A signal processing device includes a first and a second reconfigurable circuit whose logic configuration can be changed. With the reconfigurable circuits sequentially reconfigured, the signal processing device conducts processes regarding signals transmitted to and from a connected external device. At a first temporal point that is after completion of reconfiguration of the first reconfigurable circuit based on the first configuration information and before completion of reconfiguration of the second reconfigurable circuit based on the second reconfigurable circuit, a signal transmission path is formed between an external interface connected to the external device and an internal interface connected to an internal device, with the first reconfigurable circuit inserted into the signal transmission path. At a second temporal point that is after completion of the reconfiguration of the second reconfigurable circuit, the second configurable circuit is inserted in the signal transmission path between the first reconfigurable circuit and the internal interface.
摘要翻译：信号处理装置包括可以改变其逻辑配置的第一和第二可重构电路。利用可重新配置的电路顺序重新配置，信号处理设备对与所连接的外部设备相连的信号进行传输。在基于第一配置信息完成第一可重新配置电路的完成之后的第一时间点和基于第二可重配置电路的第二可重新配置电路的重新配置完成之前，在连接的外部接口之间形成信号传输路径连接到外部设备和连接到内部设备的内部接口，其中第一可重新配置电路插入到信号传输路径中。在完成第二可重构电路的重新配置之后的第二时间点，第二可配置电路插入在第一可重新配置电路和内部接口之间的信号传输路径中。

55. 发明申请

US20090307470A1 MULTI THREAD PROCESSOR HAVING DYNAMIC RECONFIGURATION LOGIC CIRCUIT 有权
标题翻译：具有动态重构逻辑电路的多线程处理器
公开(公告)号：US20090307470A1
公开(公告)日：2009-12-10
申请号：US12093884
申请日：2006-11-21
申请人： Masaki Maeda , Hideshi Nishida , Yorihiko Wakayama
发明人： Masaki Maeda , Hideshi Nishida , Yorihiko Wakayama
IPC分类号： G06F9/318
CPC分类号： G06F15/7867
摘要： A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and causes concurrent execution of an operation cell having a configuration for the current thread and (ii) an operation cell having a configuration for the next thread.
摘要翻译：根据本发明的处理器在分配给它的每个时间段周期性地执行多个线程。处理器为每个线程存储操作单元的配置信息。每个线程使得执行不同的预定数量的操作单元串联，并且在分配给当前线程的时间段内，基于存储的一条配置信息，连续地重新配置已经完成其最后操作的操作单元对应于下一个线程的操作单元，并且使具有当前线程的配置的操作单元并行执行，以及（ii）具有下一个线程的配置的操作单元。

56. 发明申请

US20080247461A1 Image Encoding Device 有权
标题翻译：图像编码装置
公开(公告)号：US20080247461A1
公开(公告)日：2008-10-09
申请号：US11662783
申请日：2005-09-05
申请人： Hideshi Nishida
发明人： Hideshi Nishida
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/58 , H04N19/127 , H04N19/137 , H04N19/157 , H04N19/172 , H04N19/51 , H04N19/57 , H04N19/61
摘要： In an image encoding device (100) that compression encodes moving pictures, a moving picture count acquisition unit (110) acquires a moving picture count of encoding target moving pictures corresponding to an arbitrary number of input moving pictures, a moving picture acquisition unit (120) acquires one or plural encoding target moving pictures, a processing method designation unit (130), in accordance with the acquired count, designates processing methods relating to encoding processing that affect a computation amount, for example, processing methods relating to a reference image frame count upper limit or a motion vector range, such that the greater the moving picture count is, the smaller the computation amount is, and an encoding processing unit (140) performs encoding processing with respect to the acquired one or plural moving pictures, using time division when the plural moving pictures are plural. The encoding unit (140) performs encoding processing using the designated methods.
摘要翻译：在对运动图像进行压缩编码的图像编码装置（100）中，运动图像计数获取部（110）获取与任意数量的输入运动图像对应的编码目标运动图像的运动图像数，运动图像获取部）获取一个或多个编码对象运动图像，根据获取的计数，处理方法指定单元（130）指定与影响计算量的编码处理相关的处理方法，例如，与参考图像帧有关的处理方法计数上限或运动矢量范围，使得运动图像数量越大计算量越小，并且编码处理单元（140）使用时间对所获取的一个或多个运动图像执行编码处理当多个运动图像是多个时分割。编码单元（140）使用指定的方法进行编码处理。

57. 发明申请

US20080201560A1 VERY LONG INSTRUCTION WORD (VLIW) COMPUTER HAVING EFFICIENT INSTRUCTION CODE FORMAT 有权
标题翻译：具有有效指导代码格式的非常长的指令词（VLIW）计算机
公开(公告)号：US20080201560A1
公开(公告)日：2008-08-21
申请号：US12103372
申请日：2008-04-15
申请人： Takahiro KAGEYAMA , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
发明人： Takahiro KAGEYAMA , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/30156 , G06F9/3016 , G06F9/3822 , G06F9/3885
摘要： A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
摘要翻译：具有缩小尺寸的指令集的超长指令字（VLIW）处理器，导致指定寄存器所需的少量位。 VLIW处理器包括寄存器文件和第一至第三操作单元，并且执行非常长的指令字。此外，非常长的指令字包括指定寄存器文件中的至少一个寄存器和多个指令的寄存器指定字段。每个指令的操作数包括位src 1，src 2和dst，它们指示由寄存器指定字段指定的寄存器是否用作源寄存器和目标寄存器。

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