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    • 53. 发明申请
    • Image compression and expansion device
    • 图像压缩和扩展设备
    • US20050094008A1
    • 2005-05-05
    • US10976766
    • 2004-11-01
    • Gen SasakiTakashi MatsutaniYusuke Nara
    • Gen SasakiTakashi MatsutaniYusuke Nara
    • H04N11/04H04N5/228H04N11/20H04N5/335
    • H04N19/40
    • RGB image data outputted from an ADC (3) is processed in an SPU (42) and an RPU (43) and then buffered into a memory (48) as YUV image data. The YUV image data is outputted from a YUV output unit (45), encoded by an image compression and expansion chip (5A) and transmitted to a main chip (4) by a DMAC (52). On the other hand, compressed moving image data stored in the memory (48) is transmitted to the image compression and expansion chip (5A) through the control by a DMAC (44), decoded therein, then converted into RGB image data in an RGB sampling unit (54) and inputted to the main chip (4) by the SPU (42) through a data line (14). With such a construction, it is possible to provide a circuit for compression and expansion, which allows connection with a main processing chip having no YUV input circuit without increasing circuit scale, maintaining general versatility of those circuits.
    • 在SPU(42)和RPU(43)中处理从ADC(3)输出的RGB图像数据,然后作为YUV图像数据缓冲到存储器(48)中。 YUV图像数据从图像压缩和扩展芯片(5A)编码的YUV输出单元(45)输出,并通过DMAC(52)发送到主芯片(4)。 另一方面,存储在存储器(48)中的压缩运动图像数据通过DMAC(44)的控制被传送到图像压缩和扩展芯片(5A),在其中解码,然后转换为RGB图像数据 RGB采样单元(54),并通过数据线(14)由SPU(42)输入到主芯片(4)。 通过这样的结构,可以提供用于压缩和扩展的电路,其允许与不具有YUV输入电路的主处理芯片连接而不增加电路规模,从而保持这些电路的通用性。
    • 55. 发明授权
    • Memory control circuit and control system for a plurality of memories interconnected via plural logic interfaces
    • 用于通过多个逻辑接口互连的多个存储器的存储器控​​制电路和控制系统
    • US06721212B2
    • 2004-04-13
    • US10334893
    • 2003-01-02
    • Gen Sasaki
    • Gen Sasaki
    • G11C710
    • G06F13/1684Y02D10/14
    • A memory control circuit includes a controller (1A) for controlling a RAM (13) conforming to the standard where source voltage is 2.5 V (SSTL2 standard), and a nonvolatile memory (14) conforming to the standard where source voltage is 3.3 V (LVTTL standard) via a control bus (10) and data buses (11, 12). The control bus (10) for transmitting an address signal and a control signal is shared by these memories (13, 14). The controller (1A) converts internal signals to signals conforming to the standard where source voltage is 2.5 V and outputs the converted signals to the control bus (10). The data buses (11, 12) are provided for the respective memories (13, 14) independently. The number of signal lines can be reduced, and it is possible to prevent signals at high voltage level outputted from the nonvolatile memory (14) from being applied to the RAM (13) driven at low voltages, to cause an occurrence of malfunction at the RAM (13).
    • 存储器控制电路包括用于控制符合源电压为2.5V的标准(SSTL2标准)的RAM(13)的控制器(1A)和符合源电压为3.3V的标准的非易失性存储器(14) LVTTL标准)经由控制总线(10)和数据总线(11,12)。 用于发送地址信号和控制信号的控制总线(10)由这些存储器(13,14)共享。 控制器(1A)将内部信号转换为符合标准的信号,其中源电压为2.5V,并将转换的信号输出到控制总线(10)。 数据总线(11,12)独立地为各个存储器(13,14)提供。 可以减少信号线的数量,并且可以防止从非易失性存储器(14)输出的高电压电平被施加到以低电压驱动的RAM(13),从而导致在 RAM(13)。
    • 56. 发明授权
    • Data conversion circuit, digital camera and data conversion method
    • 数据转换电路,数码相机和数据转换方法
    • US06677867B2
    • 2004-01-13
    • US10360797
    • 2003-02-10
    • Gen Sasaki
    • Gen Sasaki
    • H03M740
    • H04N1/407
    • An object of the present invention is to reduce bit depth and word number of a LUT memory 12 as small as possible, while obtaining &ggr; conversion output data with accuracy superior to the bit depth. Outputting table output data Dout0 and Dout1 which are associated with first table input data RA0 addressed and inputted to the LUT memory 12 and second table input data RA1 obtained by adding “1” thereto, and interpolating them outside the LUT memory 12, thereby obtaining output data having a larger bit depth than the LUT memory 12. At this time, the speed of signal processing is improved by employing a dual port memory as the LUT memory 12 or using a register group for the single port memory. Also, when the second table input data RA1 overflows, a specific value is employed as an alternative.
    • 本发明的目的是尽可能地减小LUT存储器12的位深度和字数,同时获得比位深度更精确的伽马转换输出数据。 将与寻址并输入到LUT存储器12的第一表输入数据RA0相关联的输出表输出数据Dout0和Dout1以及通过将“1”相加并将其内插到LUT存储器12之外的第二表输入数据RA1,从而获得输出 数据具有比LUT存储器12更大的位深度。此时,通过采用双端口存储器作为LUT存储器12或者使用用于单端口存储器的寄存器组来提高信号处理速度。 此外,当第二表输入数据RA1溢出时,采用特定值作为替代。
    • 60. 发明授权
    • Image distortion processing apparatus, and method of operating an image distortion processing apparatus
    • 图像失真处理装置以及操作图像失真处理装置的方法
    • US08723989B2
    • 2014-05-13
    • US12949181
    • 2010-11-18
    • Kazuma TakahashiGen Sasaki
    • Kazuma TakahashiGen Sasaki
    • H04N5/262
    • H04N5/3572G06T5/006G06T2207/20021
    • An image processing apparatus includes: a relative coordinate acquisition part acquiring a corresponding position on an input image with respect to a predetermined pixel on an output image; a first storage part storing position information of the corresponding position; a reading control part causing pixel values of input pixels on the input image to be sequentially read; an organization part organizing a set of grid points formed of input pixels among input pixels read by the reading control part; a judgment part judging, based on the position information, whether or not pixel values of pixels in the vicinity of the corresponding position used in calculating a pixel value of the predetermined pixel have been read; a local memory storing, in a case where judgment is made that pixels in the vicinity of the corresponding position have been read, pixel values of pixels forming the set of grid points as pixel values of surrounding pixels regarding the predetermined pixel; and a pixel value calculation part calculating a pixel value of the predetermined pixel by interpolation using the pixel values of the surrounding pixels.
    • 一种图像处理装置包括:相对坐标获取部分,获取输出图像上相对于输出图像上的预定像素的对应位置; 存储对应位置的位置信息的第一存储部; 读取控制部分,其使输入图像上的输入像素的像素值顺序读取; 组织部分,组织由读取控制部分读取的输入像素之中的输入像素形成的一组网格点; 判断部分,基于位置信息,判断在计算所述预定像素的像素值时使用的相应位置附近的像素的像素值是否被读取; 局部存储器,在判断已经读取相应位置附近的像素的情况下,存储形成该组栅格点的像素的像素值,作为与预定像素相关的周围像素的像素值; 以及像素值计算部分,通过使用周围像素的像素值进行插值来计算预定像素的像素值。