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51. 发明申请

US20120201070A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA WRITING METHOD THEREFOR 有权
标题翻译：非易失性半导体存储器件及其数据写入方法
公开(公告)号：US20120201070A1
公开(公告)日：2012-08-09
申请号：US13415953
申请日：2012-03-09
申请人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi Maejima , Katsuaki Isobe , Hideo Mukai
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C7/00 , G11C13/0004 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor storage device includes first and second intersecting wires; a electrically rewritable memory cell disposed at each intersection of the first second wires, including a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire to a standby voltage larger than a reference voltage prior to programming a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying to the selected first wire a program voltage for programming of the selected variable resistor and applying to the non-selected second wire a control voltage which prevents the rectifying device from turning ON.
摘要翻译：非易失性半导体存储装置包括第一和第二相交线; 在第一第二导线的交点设置有包含用于将电阻值作为数据非易失性地存储的可变电阻器和整流装置的电可重写存储单元串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。在通过将参考电压提供给未选择的第一线和所选择的第二线之前，控制电路将未选择的第二线预充电至大于参考电压的待机电压，然后再对连接到所选择的第一和第二线的可变电阻进行编程，向所选择的第一线施加用于对所选择的可变电阻器进行编程的编程电压，并向未选择的第二线施加防止整流装置导通的控制电压。

52. 发明授权

US07978517B2 NAND flash memory 失效
标题翻译： NAND闪存
公开(公告)号：US07978517B2
公开(公告)日：2011-07-12
申请号：US12719686
申请日：2010-03-08
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C8/10 , G11C16/0483
摘要： A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of the memory cell units having a plurality of electrically rewritable memory cells that are connected to each other, wherein a bit line that is selected by a sense amplifier is charged in a state where a drain-side select gate line, a source-side select gate line and a p-type semiconductor substrate are set at a ground potential, and source lines, n-type wells, p-type wells, and a bit line that is not selected by the sense amplifier are in a floating state.
摘要翻译：在选择的位线和非选择的位线彼此相邻时读取的NAND快闪存储器具有存储单元阵列，其具有多个块，每个块由多个存储单元单元组成，每个块由多个存储单元单元组成所述存储单元单元具有彼此连接的多个电可重写存储单元，其中由读出放大器选择的位线在漏极侧选择栅极线，源极侧选择栅极线路和p型半导体衬底设置为接地电位，源极线，n型阱，p型阱和未被读出放大器选择的位线处于浮置状态。

53. 发明授权

US07800935B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07800935B2
公开(公告)日：2010-09-21
申请号：US12252675
申请日：2008-10-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
发明人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2211/5642 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.
摘要翻译：一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 ＆Dgr; R2的关系。

54. 发明申请

US20100097860A1 NAND FLASH MEMORY 有权
标题翻译： NAND闪存
公开(公告)号：US20100097860A1
公开(公告)日：2010-04-22
申请号：US12642503
申请日：2009-12-18
申请人： Hiroshi MAEJIMA , Katsuaki Isobe
发明人： Hiroshi MAEJIMA , Katsuaki Isobe
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

55. 发明申请

US20100097832A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100097832A1
公开(公告)日：2010-04-22
申请号：US12580795
申请日：2009-10-16
申请人： Hideo MUKAI , Hiroshi Maejima , Katsuaki Isobe
发明人： Hideo MUKAI , Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C11/00 , G11C5/02 , G11C5/06
CPC分类号： G11C8/14 , G11C7/18 , G11C8/12 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C2213/31 , G11C2213/72
摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.
摘要翻译：一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及存储单元连接在第一和第二线之间。该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。存储单元通过连接到从MAT中选择的每个第一行形成页面。该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。

56. 发明授权

US07660157B2 NAND flash memory 有权
标题翻译： NAND闪存
公开(公告)号：US07660157B2
公开(公告)日：2010-02-09
申请号：US11873859
申请日：2007-10-17
申请人： Hiroshi Maejima , Katsuaki Isobe
发明人： Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, including a memory cell array, a row decoder, and a sense amplifier. In a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by the row decoder, a drain-side select gate line and the source-side select gate line are charged to a third voltage, which is higher than the ground potential and is equal to or lower than the second voltage.
摘要翻译：一种NAND闪存，包括存储单元阵列，行解码器和读出放大器。在读取操作中，将p型半导体衬底设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电至第二电压，位于接地电位和第一电压之间，并且在未被行解码器选择的块中，漏极侧选择栅极线和源极侧选择栅极线被充电到高于地的第三电压并且等于或低于第二电压。

57. 发明申请

US20090207647A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA WRITING METHOD THEREFOR 有权
标题翻译：非易失性半导体存储器件及其数据写入方法
公开(公告)号：US20090207647A1
公开(公告)日：2009-08-20
申请号：US12370111
申请日：2009-02-12
申请人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
发明人： Hiroshi MAEJIMA , Katsuaki Isobe , Hideo Mukai
IPC分类号： G11C11/00 , G11C7/00 , G11C11/416
CPC分类号： G11C13/0007 , G11C7/00 , G11C13/0004 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor storage device comprises: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire up to a standby voltage larger than a reference voltage prior to a set operation for programming only a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying a program voltage necessary for programming of the selected variable resistor based on the reference voltage to the selected first wire and applying a control voltage which prevents the rectifying device from turning ON based on the program voltage to the non-selected second wire.
摘要翻译：非易失性半导体存储装置包括：第一线和彼此交叉的第二线; 存储单元，其配置在所述第一配线和所述第二配线的各交叉点并且是电可重写的，并且其中存储用作非易失性数据的电阻值的可变电阻器和整流装置串联连接; 以及控制电路，其向第一和第二导线施加写入数据所需的电压。控制电路在设置操作之前将未选择的第二线预充电到大于参考电压的待机电压，以仅通过将参考电压提供给未选择的第一线来仅编程连接到所选择的第一和第二线的可变电阻器和所选择的第二线路，基于参考电压将所选择的可变电阻器编程所需的编程电压施加到所选择的第一线路，并施加防止整流装置导通的控制电压，选择第二根线。

58. 发明申请

US20060034120A1 Non-volatile semiconductor memory device 有权
公开(公告)号：US20060034120A1
公开(公告)日：2006-02-16
申请号：US11193442
申请日：2005-08-01
申请人： Katsuaki Isobe , Masatsugu Kojima
发明人： Katsuaki Isobe , Masatsugu Kojima
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C16/225
摘要： When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.

59. 发明申请

US20050207237A1 Semiconductor memory device provided with constant-current circuit having current trimming function 失效
标题翻译：具有具有电流修整功能的恒流电路的半导体存储器件
公开(公告)号：US20050207237A1
公开(公告)日：2005-09-22
申请号：US11045383
申请日：2005-01-31
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C16/06 , G11C29/02 , H03B1/00
CPC分类号： G11C29/028 , G11C29/02 , G11C2029/5006
摘要： A semiconductor memory device includes a memory cell unit including at least one semiconductor memory cell, a voltage generating circuit which produces an operating voltage to which reference is made in performing a predetermined operation on the memory cell unit. The device further includes a constant-current circuit capable of a current trimming operation and adapted to supply a constant current to the voltage generating circuit.
摘要翻译：半导体存储器件包括存储单元单元，该存储单元单元包括至少一个半导体存储单元，产生电路的电压产生电路，该电压产生电路在对存储单元单元执行预定操作时进行参考。该装置还包括能够进行电流调整操作并适于向电压产生电路提供恒定电流的恒流电路。

60. 发明授权

US06731149B2 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
标题翻译：用于产生与时钟信号同步的信号的同步电路
公开(公告)号：US06731149B2
公开(公告)日：2004-05-04
申请号：US10003312
申请日：2001-12-06
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03K501
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.
摘要翻译：用于正向脉冲的第一延迟线和用于反向脉冲的第二延迟线由单位延迟元件组成。状态保持部根据沿着第一延迟线传送的正向脉冲的传送位置来确定第二延迟线上的反向脉冲的输入位置。在构成第一和第二延迟线的单位延迟元件中，可以通过增加与脉冲信号的上升相关的晶体管的电流驱动能力来提高同步精度。

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