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51. 发明授权

US5504911A Bus system servicing plural module requestors with module access identification 失效
标题翻译：总线系统服务多个具有模块访问标识的模块请求者
公开(公告)号：US5504911A
公开(公告)日：1996-04-02
申请号：US626245
申请日：1990-12-12
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G06F13/16 , G06F13/364 , G06F13/36
CPC分类号： G06F13/1605 , G06F13/364
摘要： An integrated circuit having a plurality of modules and an internal communication bus interconnecting the modules is arranged to produce an output indicating which module is granted access to the bus at the time. A control means grants to a module access to the bus in response to a request from the module on the basis of the priority of its request amongst any other requests for access. The control means produces the output indication in digital form which is multiplexed with other data from the bus at an output port of the integrated circuit.
摘要翻译：布置具有多个模块和互连模块的内部通信总线的集成电路，以产生一个输出，指示哪个模块被授权访问总线。响应于来自模块的请求，控制装置根据其请求的优先级在任何其他访问请求之间授予模块对总线的访问。控制装置产生数字形式的输出指示，该集成电路的输出端口与来自总线的其它数据多路复用。

52. 发明授权

US5339447A Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data 失效
标题翻译：使用互连的半加法器的矩阵的计数电路用于对图像数据的二进制串中的数量进行计数
公开(公告)号：US5339447A
公开(公告)日：1994-08-16
申请号：US437857
申请日：1989-11-17
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G06F7/60 , G06F7/50
CPC分类号： G06F7/607
摘要： In an imaging system (5310), a histogram of images may be made by counting the number of "one" pixels in a matrix of image pixels. A ones counting circuit (5320) is provided to produce a binary number Y indicative of the number of "ones" in an input binary string X. The circuit (5320) comprises a matrix (5424) of counting cells (5426) arranged and interconnected in rows and columns. Each of the counting cells (5426) includes an AND gate (5428) coupled to an exclusive-OR (XOR) gate (5430). A binary string having X.sub.N bits may be thus counted employing a matrix having M rows, where M=log2(X.sub.N +1) rounded up to the nearest integer and N columns. An alternative embodiment employs a minimized matrix. This minimized matrix has M rows, where M=log2(X.sub.N +1) rounded up to the nearest integer. The minimized matrix has N=X.sub.N -2.sup.r elements in each row, where r is the row number ranging from zero for the first row to (M-1) for the last row.
摘要翻译：在成像系统（5310）中，可以通过对图像像素的矩阵中的“一个”像素的数量进行计数来进行图像的直方图。提供一个计数电路（5320）以产生指示输入二进制串X中的“1”个数的二进制数字Y.电路（5320）包括布置和互连的计数单元（5426）的矩阵（5424）在行和列。每个计数单元（5426）包括耦合到异或（XOR）门（5430）的与门（5428）。可以使用具有M行的矩阵来计数具有XN位的二进制串，其中M = log2（XN + 1）向上舍入到最接近的整数和N列。替代实施例采用最小化的矩阵。该最小化矩阵具有M行，其中M = log2（XN + 1）向上取整为最接近的整数。最小化矩阵在每行中具有N = XN-2r个元素，其中r是从第一行的零到最后一行的（M-1）的行号。

53. 发明授权

US4956850A Digital electronic system 失效
标题翻译：数字电子系统
公开(公告)号：US4956850A
公开(公告)日：1990-09-11
申请号：US278710
申请日：1988-12-01
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： H03K19/0175 , H04L12/40
CPC分类号： H03K19/017545
摘要： A bus interconnecting a plurality of digital modules is divided into sections interconnected by buffers so that the loading on the drive circuits of the modules is reduced. Unidirectional buffers can be used where a bus section is connected only to modules driving the bus section or only to modules receiving signals from the bus section. A bidirectional buffer is clocked so that it is only capable of signal transmission in either direction during a clock pluse, thereby eliminating the regenerative feedback which would cause the buffer to hold a signal value. The logical sense of signals used by the bus sections may all be the same or some sections may use signals of the opposite logical sense; inverting and non-inverting buffers are used as required. A gated buffer may be provided enabling signal transmission from one bus section to another to be blocked. The modules, bus and buffers may be formed as an integrated circuit.
摘要翻译：将多个数字模块互连的总线被分成由缓冲器互连的部分，从而减少模块驱动电路上的负载。只有总线部分只连接到驱动总线部分的模块，或仅连接到从总线部分接收信号的模块，则可以使用单向缓冲器。双向缓冲器被计时，使得其仅在时钟脉冲期间能够在任一方向上进行信号传输，从而消除将导致缓冲器保持信号值的再生反馈。总线部分使用的信号的逻辑意义可以是相同的，或者一些部分可以使用相反的逻辑意义的信号; 根据需要使用反相和非反相缓冲器。可以提供门控缓冲器，使得能够从一个总线部分到另一个总线部分的信号传输被阻塞。模块，总线和缓冲器可以形成为集成电路。

54. 发明授权

US06948050B1 Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware 失效
标题翻译：单一集成电路体现了具有单独指令处理硬件的双异质处理器
公开(公告)号：US06948050B1
公开(公告)日：2005-09-20
申请号：US09875136
申请日：2001-06-06
申请人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
IPC分类号： G06F9/38 , G06F15/16 , G06F15/173
CPC分类号： G06F9/3885 , G06F9/3851 , G06F15/17375
摘要： A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.
摘要翻译：单个集成电路包括在不相交的程序和数据上独立操作的不同指令集上操作的第一和第二数据处理器。单个集成电路优选地包括外部接口，共享数据传输控制器和被分成多个可独立存取的存储体的共享存储器。两个数据处理器优选地是数字信号处理器（DSP）和精简指令集计算机（RISC）处理器。 DSP和RISC处理器被适当地编程以执行计算机图像处理的不同方面。

55. 发明授权

US6067613A Rotation register for orthogonal data transformation 失效
标题翻译：旋转寄存器进行正交数据转换
公开(公告)号：US6067613A
公开(公告)日：2000-05-23
申请号：US159346
申请日：1993-11-30
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G09G5/39 , G06F3/153 , G06F9/30 , G06F9/315 , G06F17/14 , G11C19/00 , G06F15/00
CPC分类号： G06F9/30032 , G06F17/147 , G06F9/30036 , G06F9/30098 , G06F9/30141 , G11C19/00
摘要： A data processing apparatus (71) includes a data processor bus (103), the rotation register (208) and a register selection circuit. The rotation register (208) is embodied by a plurality of data registers (200) each having a plurality of equal bit groups. The number of bits within each bit group of each data register preferably equals the number N of data registers. The register selection circuit permits normal register reads and writes via the data processor bus. The register selection circuit permits special rotational data accesses. In a rotation read mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for read access. In a rotation write mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for write access. The data registers (200) are connected together in a loop (208). The most significant bit of each data register connected to the least significant bit of a sequential data register, with the last data register is connected to the first data register. In a register rotation mode the register selection circuit rotates bits in each data register in around the loop. This rotation is preferably by one bit upon each execution of a register rotation instruction.
摘要翻译：数据处理装置（71）包括数据处理器总线（103），旋转寄存器（208）和寄存器选择电路。旋转寄存器（208）由多个数据寄存器（200）实现，每个数据寄存器（200）具有多个相等的位组。每个数据寄存器的每个位组内的位数优选等于数据寄存器的数量N. 寄存器选择电路允许通过数据处理器总线进行正常寄存器读和写操作。寄存器选择电路允许特殊的旋转数据访问。在旋转读取模式中，寄存器选择电路从每个部分中的预定位置选择用于读取访问的每个数据寄存器的不连续位。在旋转写入模式中，寄存器选择电路为每个用于写入的数据寄存器的每个部分中的预定位置选择非连续位。数据寄存器（200）以循环（208）连接在一起。连接到顺序数据寄存器的最低有效位的每个数据寄存器的最高有效位与最后一个数据寄存器连接到第一个数据寄存器。在寄存器旋转模式下，寄存器选择电路在循环周围旋转每个数据寄存器中的位。每次执行寄存器旋转指令时，该旋转优选为一位。

56. 发明授权

US5922070A Pipelined data processing including program counter recycling 失效
标题翻译：流水线数据处理，包括程序计数器回收
公开(公告)号：US5922070A
公开(公告)日：1999-07-13
申请号：US350640
申请日：1994-12-07
申请人： Gary L. Swoboda , Mark R. Hammes , Douglas Deao , Keith Balmer , Nick Ing-Simmons
发明人： Gary L. Swoboda , Mark R. Hammes , Douglas Deao , Keith Balmer , Nick Ing-Simmons
IPC分类号： G06F9/38 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3636 , G06F9/3842 , G06F9/3863 , G06F9/3867
摘要： In a pipeline data processor (11), an address pipeline (39, 41) id provided to hold the addresses of the instructions presently in the instruction pipeline (23, 25). The address pipeline facilitates tracing only executed instructions, and permits stopping the data processor during a branch delay slot without losing the branch information.
摘要翻译：在流水线数据处理器（11）中，提供用于保持当前在指令流水线（23,25）中的指令的地址的地址流水线（39,41）id。地址管线便于跟踪执行的指令，并且允许在分支延迟时隙期间停止数据处理器而不丢失分支信息。

57. 发明授权

US5881272A Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors on write to program counter of one processor 失效
标题翻译：同步MIMD多处理系统和方法禁止在其他处理器上的指令读取到一个处理器的程序计数器
公开(公告)号：US5881272A
公开(公告)日：1999-03-09
申请号：US922152
申请日：1997-09-02
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G06F9/30 , G06F9/312 , G06F9/315 , G06F9/318 , G06F9/355 , G06F9/38 , G06F15/16
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30087 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30192 , G06F9/321 , G06F9/325 , G06F9/355 , G06F9/3832 , G06F9/3885
摘要： A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.
摘要翻译：在一个实施例中，多处理器系统被布置为图像和图形处理器。处理器的结构与几个单独的处理器都具有到几个存储器的通信链接。各个处理器可以逐周期地分组在任何配置中，与该组中的其他处理器同步（但是来自不同的指令流）运行。可以同时形成多个这样的同步组。交叉开关用于建立处理器存储器链路，并且整个图像处理器，包括各个处理器，交叉开关和存储器都包含在单个硅芯片上。

58. 发明授权

US5696913A Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor 失效
标题翻译：具有多个具有与每个处理器对应的统一地址空间的存储器的多处理系统中的唯一处理器标识符
公开(公告)号：US5696913A
公开(公告)日：1997-12-09
申请号：US472827
申请日：1995-06-07
申请人： Robert J. Gove , Karl Marion Guttag , Keith Balmer , Nicholas Kerin Ing-Simmons
发明人： Robert J. Gove , Karl Marion Guttag , Keith Balmer , Nicholas Kerin Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F15/17375 , G06F12/0284
摘要： A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. Each processor has a register with a plurality of read only bits which uniquely identify that processor within the multi-processing system. The processor may employ this unique processor identifier to compute the base address corresponding to that processor. This enables programs which may execute independently of the processor within the multi-processing system.
摘要翻译：多处理系统包括多个存储器和多个处理器。每个存储器具有单个存储器地址空间的唯一可寻址存储器部分。每个处理器具有预定的多个对应的存储器。这些相应的存储器在所述单个存储器地址空间内具有对应的基址。根据接收到的指令，处理器产生用于对存储在所述多个存储器中的数据进行读/写访问的地址。连接到存储器和处理器的开关矩阵响应由处理器产生的地址，以选择性地在该处理器与其唯一可寻址存储器部分包含该地址的存储器之间路由数据。每个处理器具有一个具有唯一地识别多处理系统内的处理器的多个只读位的寄存器。处理器可以采用这种唯一的处理器标识符来计算对应于该处理器的基地址。这使得能够独立于多处理系统内的处理器执行的程序。

59. 发明授权

US5606677A Packed word pair multiply operation forming output including most significant bits of product and other bits of one input 失效
标题翻译：封装字对乘法运算形成输出，包括产品的最高有效位和一个输入的其他位
公开(公告)号：US5606677A
公开(公告)日：1997-02-25
申请号：US472828
申请日：1995-06-07
申请人： Keith Balmer , Christopher J. Read
发明人： Keith Balmer , Christopher J. Read
IPC分类号： G06F7/52 , G06F9/302 , G06F7/44
CPC分类号： G06F7/5324 , G06F7/5336 , G06F9/30014 , G06F9/30036 , G06F2207/382 , G06F2207/3828 , G06F7/49963
摘要： This invention is a method and apparatus for multiplication which enables two factors to be packed into the same size data word as the product. The invention partitions two N bit buses (210, 202) into a first set of M bits and a second set of L bits. In the preferred embodiment the first set of M bits is N/2 most significant bits and the second set of L bits in N/2 least significant bits. Thus N=M+L and M=L. A multiplier (220) multiplies the second sets of L bits of each of the N bit numbers. This results in a product having up to 2L bits. The invention forms an output word having a first set of L bits being the most significant L bits of the product and a second set of M bits being the first set of M bits of the first N bit data word. In the preferred embodiment, a multiplexer (221) selects between the full product of 2L bits and the packed word output. The product may be scaled prior to partitioning via a left shifter (224) which shifts the product a selected number of bit positions. The invention preferably also includes rounding the most significant half of the product using an adder (226). This invention enables multiplication of respective first and second sets of bits of a first number by respective second and third numbers, resulting in a single packed word resultant. This process includes two passes through the multiplier (220). The final resultant has a first set of bits corresponding to the most significant half of the second product and a second set of bits corresponding to the first set product from the intermediate resultant. In the preferred embodiment of this invention, the multiplier (220) is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.
摘要翻译：本发明是一种用于乘法的方法和装置，其使两个因素能够被打包成与产品相同大小的数据字。本发明将两个N位总线（210,202）分成第一组M位和第二组L位。在优选实施例中，第一组M位是N / 2个最高有效位，并且N / 2个最低有效位中的第二组L位。因此N = M + L和M = L。乘法器（220）将N位数中的每一个的第二组L位相乘。这导致产品具有高达2L的位。本发明形成具有产品的最高有效L位的第一组L位和第一N位数据字M位的第一组M位的输出字。在优选实施例中，多路复用器（221）在2L位的全乘积和打包字输出之间进行选择。产品可以在经由左移位器（224）进行分割之前进行缩放，左移位器将产品移动到选定数量的位位置。本发明还优选地还包括使用加法器（226）对产品的最重要的一半舍入。本发明使得能够通过相应的第二和第三数字来乘以第一数字的相应的第一和第二组位，导致单个打包字的结果。该过程包括通过乘法器（220）的两次通过。最终结果具有对应于第二乘积的最高有效半部分的第一组位，以及对应于来自中间结果的第一集合乘积的第二组位。在本发明的优选实施例中，乘法器（220）被实现在至少一个数字图像/图形处理器（71,72,73,74）中，作为形成在单个集成电路中使用的多处理器（100）的一部分，图像处理。

60. 发明授权

US07047284B1 Transfer request bus node for transfer controller with hub and ports 有权
标题翻译：用于具有集线器和端口的传输控制器的传输请求总线节点
公开(公告)号：US07047284B1
公开(公告)日：2006-05-16
申请号：US09713440
申请日：2000-11-15
申请人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
发明人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
IPC分类号： G06F15/177
CPC分类号： G06F13/37
摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译：描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

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