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51. 发明申请

US20120286364A1 Integrated Circuit Diode 有权
标题翻译：集成电路二极管
公开(公告)号：US20120286364A1
公开(公告)日：2012-11-15
申请号：US13104542
申请日：2011-05-10
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/0727 , H01L21/823418 , H01L21/84 , H01L27/0629 , H01L27/1203
摘要： A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.
摘要翻译：一种方法包括在半导体衬底中形成隔离区以限定第一场效应晶体管（FET）区域，第二FET区域和二极管区域，在第一FET区域中形成第一栅极堆叠，在第二FET区域中形成第二栅极堆叠 FET区域，在所述第二FET区域和所述第二栅极堆叠上形成间隔材料层，在所述第一FET区域中形成第一源极区域和第一漏极区域，以及使用第一外延生长工艺在所述二极管区域中形成第一二极管层在所述第一源极区域，所述第一漏极区域，所述第一栅极堆叠层和所述第一二极管层的一部分上形成硬掩模层，以及在所述第一FET区域中形成第二源极区域和第二漏极区域，以及在所述第一FET区域中形成第二二极管层使用第二外延生长工艺在第一二极管层上。

52. 发明申请

US20120235239A1 HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION 有权
标题翻译：具有排水侧肖特基结的混合MOSFET结构
公开(公告)号：US20120235239A1
公开(公告)日：2012-09-20
申请号：US13049491
申请日：2011-03-16
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/336 , H01L29/78
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/26586 , H01L21/823814 , H01L21/823878 , H01L29/7839
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化的栅极结构，在邻近栅极结构的源极侧的半导体衬底上形成凸起的源极区域，并在图案化的栅极上形成凸起的源极区域上的硅化物接触并且在与栅极结构的漏极侧相邻的半导体衬底上。因此，限定了具有漏极侧肖特基接触和升高的源极侧欧姆接触的混合场效应晶体管（FET）结构。

53. 发明授权

US08835900B2 Highly scaled ETSOI floating body memory and memory circuit 有权
标题翻译：高度ETSOI浮体和内存电路
公开(公告)号：US08835900B2
公开(公告)日：2014-09-16
申请号：US13154677
申请日：2011-06-07
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/06 , H01L27/12 , H01L21/336
CPC分类号： H01L29/7841 , H01L21/8252 , H01L21/8254 , H01L21/8258 , H01L21/84 , H01L27/0605 , H01L27/10802 , H01L27/1203
摘要： A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction.
摘要翻译：一种用于制造浮体存储单元的浮体存储单元，存储器电路和方法。浮体存储单元包括具有耦合到第二半导体的第一半导体的双层异质结。第一半导体和第二半导体具有不同的能带隙。浮体存储单元包括掩埋绝缘体层。浮体存储单元包括通过至少掩埋绝缘层与双层异质结的第二半导体分离的背晶体管栅极。浮体存储单元还包括耦合到双层异质结的第一半导体的前晶体管栅极。

54. 发明授权

US08610233B2 Hybrid MOSFET structure having drain side schottky junction 有权
标题翻译：具有漏极侧肖特基结的混合MOSFET结构
公开(公告)号：US08610233B2
公开(公告)日：2013-12-17
申请号：US13049491
申请日：2011-03-16
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L31/102
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/26586 , H01L21/823814 , H01L21/823878 , H01L29/7839
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化的栅极结构，在邻近栅极结构的源极侧的半导体衬底上形成凸起的源极区域，并在图案化的栅极上形成凸起的源极区域上的硅化物接触并且在与栅极结构的漏极侧相邻的半导体衬底上。因此，限定了具有漏极侧肖特基接触和升高的源极侧欧姆接触的混合场效应晶体管（FET）结构。

55. 发明授权

US08482078B2 Integrated circuit diode 有权
公开(公告)号：US08482078B2
公开(公告)日：2013-07-09
申请号：US13104542
申请日：2011-05-10
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/70
CPC分类号： H01L27/0727 , H01L21/823418 , H01L21/84 , H01L27/0629 , H01L27/1203
摘要： A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.

56. 发明授权

US08642415B2 Semiconductor substrate with transistors having different threshold voltages 失效
标题翻译：具有不同阈值电压的晶体管的半导体衬底
公开(公告)号：US08642415B2
公开(公告)日：2014-02-04
申请号：US13487511
申请日：2012-06-04
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.
摘要翻译：公开了一种制造半导体集成电路的方法。该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

57. 发明申请

US20120313143A1 HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT 有权
标题翻译：高分辨率ETSOI浮动体内存和存储器电路
公开(公告)号：US20120313143A1
公开(公告)日：2012-12-13
申请号：US13154677
申请日：2011-06-07
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/772 , H01L21/338
CPC分类号： H01L29/7841 , H01L21/8252 , H01L21/8254 , H01L21/8258 , H01L21/84 , H01L27/0605 , H01L27/10802 , H01L27/1203
摘要： A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction.
摘要翻译：一种用于制造浮体存储单元的浮体存储单元，存储器电路和方法。浮体存储单元包括具有耦合到第二半导体的第一半导体的双层异质结。第一半导体和第二半导体具有不同的能带隙。浮体存储单元包括掩埋绝缘体层。浮体存储单元包括通过至少掩埋绝缘层与双层异质结的第二半导体分离的背晶体管栅极。浮体存储单元还包括耦合到双层异质结的第一半导体的前晶体管栅极。

58. 发明申请

US20130292766A1 SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES 审中-公开
标题翻译：具有不同阈值电压的晶体管的半导体衬底
公开(公告)号：US20130292766A1
公开(公告)日：2013-11-07
申请号：US13463402
申请日：2012-05-03
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor integrated circuit is provided and includes a first field effect transistor (FET) device and a second FET device formed on a semiconductor substrate. The first FET device has raised source/drain (RSD) structures grown at a first height. The second FET device has RSD structures grown at a second height greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.
摘要翻译：提供了半导体集成电路，并且包括形成在半导体衬底上的第一场效应晶体管（FET）器件和第二FET器件。第一FET器件提高了在第一高度生长的源极/漏极（RSD）结构。第二FET器件具有在大于第一高度的第二高度处生长的RSD结构，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

59. 发明申请

US20130295730A1 SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES 失效
标题翻译：具有不同阈值电压的晶体管的半导体衬底
公开(公告)号：US20130295730A1
公开(公告)日：2013-11-07
申请号：US13487511
申请日：2012-06-04
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.
摘要翻译：公开了一种制造半导体集成电路的方法。该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

60. 发明申请

US20130175579A1 TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN 审中-公开
标题翻译：带有通道和放大源/漏极的晶体管
公开(公告)号：US20130175579A1
公开(公告)日：2013-07-11
申请号：US13347161
申请日：2012-01-10
申请人： Kangguo Cheng , Ali Khakifirooz , Sivananda Kanakasabapathy , Pranita Kulkarni , Balasubramanian S. Haran
发明人： Kangguo Cheng , Ali Khakifirooz , Sivananda Kanakasabapathy , Pranita Kulkarni , Balasubramanian S. Haran
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/7848 , H01L29/785
摘要： A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer.
摘要翻译：晶体管包括第一半导体层。第二半导体层位于第一半导体层上。去除第二半导体层的一部分以暴露第一半导体层的第一部分并提供第二半导体层的垂直侧壁。栅极间隔物位于第二半导体层上。栅极电介质包括位于第一半导体层的第一部分上的第一部分和与第二半导体层的垂直侧壁相邻的第二部分。栅极导体位于栅极电介质的第一部分上并邻接栅极电介质第二部分。沟道区位于第一半导体层的第一部分的至少一部分中。上升的源极/漏极区域位于第二半导体层中。凸起的源极/漏极区域的至少一部分位于栅极间隔物的下方。

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