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51. 发明授权

US08158453B2 Methods of forming silicide strapping in imager transfer gate device 有权
标题翻译：在成像器传输门装置中形成硅化物带的方法
公开(公告)号：US08158453B2
公开(公告)日：2012-04-17
申请号：US12699419
申请日：2010-02-03
申请人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
发明人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
IPC分类号： H01L21/336
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689
摘要： A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.
摘要翻译：具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

52. 发明授权

US07915056B2 Image sensor monitor structure in scribe area 失效
标题翻译：图像传感器监控结构在划片区域
公开(公告)号：US07915056B2
公开(公告)日：2011-03-29
申请号：US12051868
申请日：2008-03-20
申请人： John J. Ellis-Monaghan , Mark D. Jaffe , Sambasivan Narayan , Anthony J. Perri , Richard J. Rassel , Tian Xia
发明人： John J. Ellis-Monaghan , Mark D. Jaffe , Sambasivan Narayan , Anthony J. Perri , Richard J. Rassel , Tian Xia
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.
摘要翻译：设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

53. 发明授权

US07821553B2 Pixel array, imaging sensor including the pixel array and digital camera including the imaging sensor 有权
标题翻译：像素阵列，包括像素阵列的成像传感器和包括成像传感器的数码相机
公开(公告)号：US07821553B2
公开(公告)日：2010-10-26
申请号：US11275417
申请日：2005-12-30
申请人： John J. Ellis-Monaghan , Mark D. Jaffe , Alain Loiseau , Richard J. Rassel
发明人： John J. Ellis-Monaghan , Mark D. Jaffe , Alain Loiseau , Richard J. Rassel
IPC分类号： H04N3/14 , H04N5/335 , H04N9/04 , H04N9/083
CPC分类号： H04N9/045
摘要： A pixel array in an image sensor, the image sensor and a digital camera including the image sensor. The image sensor includes a pixel array with colored pixels and unfiltered (color filter-free) pixels. Each unfiltered pixel occupies one or more array locations. The colored pixels may be arranged in uninterrupted rows and columns with unfiltered pixels disposed between the uninterrupted rows and columns. The image sensor may in CMOS with the unfiltered pixels reducing low-light noise and improving low-light sensitivity.
摘要翻译：图像传感器中的像素阵列，图像传感器和包括图像传感器的数字照相机。图像传感器包括具有彩色像素和未滤波（无滤色器）像素的像素阵列。每个未过滤的像素占据一个或多个阵列位置。彩色像素可以布置在不间断的行和列中，其中未过滤的像素布置在不间断的行和列之间。图像传感器可以在CMOS中，未滤色像素降低低光噪声并改善低光灵敏度。

54. 发明授权

US07655966B2 High efficiency CMOS image sensor pixel employing dynamic voltage supply 有权
标题翻译：采用动态电压源的高效率CMOS图像传感器像素
公开(公告)号：US07655966B2
公开(公告)日：2010-02-02
申请号：US12050967
申请日：2008-03-19
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N3/14
CPC分类号： H04N5/361 , G06F17/5063 , H04N5/359 , H04N5/3745
摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.
摘要翻译：提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

55. 发明授权

US08405751B2 Image sensor pixel structure employing a shared floating diffusion 有权
标题翻译：采用共享浮动扩散的图像传感器像素结构
公开(公告)号：US08405751B2
公开(公告)日：2013-03-26
申请号：US12534427
申请日：2009-08-03
申请人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
发明人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
IPC分类号： H04N5/335
CPC分类号： H01L27/14609 , H01L27/14641 , H01L27/14643 , H04N5/37457
摘要： A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.
摘要翻译：图像传感器的像素结构包括具有共面且相邻的半导体表面的半导体材料部分，包括四个光电二极管，四个沟道区域和公共的浮动扩散区域。四个通道区域中的每一个直接邻接四个光电二极管和公共浮动扩散区域中的一个。四个光电二极管位于四个不同的象限内，如使用通过公共浮动扩散区域内的点作为中心轴的垂直线所限定的。公共浮动扩散区域，复位栅极晶体管，源极跟随器晶体管和行选择晶体管位于四个不同的象限内，如使用通过一个光电二极管内的点作为轴的垂直线所限定的。

56. 发明申请

US20110025892A1 IMAGE SENSOR PIXEL STRUCTURE EMPLOYING A SHARED FLOATING DIFFUSION 有权
标题翻译：图像传感器像素结构采用共享浮动扩展
公开(公告)号：US20110025892A1
公开(公告)日：2011-02-03
申请号：US12534427
申请日：2009-08-03
申请人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
发明人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
IPC分类号： H04N5/335 , H01L31/112 , G06F17/50
CPC分类号： H01L27/14609 , H01L27/14641 , H01L27/14643 , H04N5/37457
摘要： A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.
摘要翻译：图像传感器的像素结构包括具有共面且相邻的半导体表面的半导体材料部分，包括四个光电二极管，四个沟道区域和公共的浮动扩散区域。四个通道区域中的每一个直接邻接四个光电二极管和公共浮动扩散区域中的一个。四个光电二极管位于四个不同的象限内，如使用通过公共浮动扩散区域内的点作为中心轴的垂直线所限定的。公共浮动扩散区域，复位栅极晶体管，源极跟随器晶体管和行选择晶体管位于四个不同的象限内，如使用通过一个光电二极管内的点作为轴的垂直线所限定的。

57. 发明授权

US07703060B2 Stitched IC layout methods, systems and program product 失效
标题翻译：拼接IC布局方法，系统和程序产品
公开(公告)号：US07703060B2
公开(公告)日：2010-04-20
申请号：US11678069
申请日：2007-02-23
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout includes for at least one stitched region of a plurality of stitched regions: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithographic tool field at the second entity.
摘要翻译：公布了拼接集成电路（IC）芯片布局方法，系统和程序产品。在一个实施例中，一种方法包括从第一实体获得超过第二实体上的光刻工具区域的尺寸的IC芯片布局的电路设计，其中IC芯片布局包括用于多个缝合区域：识别发生缝合的至少一个缝合区域的边界的边界标识和指示所述至少一个缝合区域是否是以下之一的类型指示器：冗余且唯一; 将IC芯片布局解剖为在第二实体处表示为唯一或冗余的缝合区域; 以及基于所述多个缝合区域在所述第二实体处产生光刻掩模版，所述光刻掩模版具有适合在所述第二实体处的所述光刻工具区域的尺寸内的尺寸。

58. 发明申请

US20090276739A1 IC CHIP AND DESIGN STRUCTURE INCLUDING STITCHED CIRCUITRY REGION BOUNDARY IDENTIFICATION 有权
标题翻译： IC芯片和设计结构，包括纹路电路区域边界识别
公开(公告)号：US20090276739A1
公开(公告)日：2009-11-05
申请号：US12112336
申请日：2008-04-30
申请人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
发明人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译：针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。

59. 发明授权

US08009215B2 Pixel sensor cell with frame storage capability 有权
标题翻译：具有帧存储能力的像素传感器单元
公开(公告)号：US08009215B2
公开(公告)日：2011-08-30
申请号：US12174264
申请日：2008-07-16
申请人： James W. Adkisson , John J. Ellis-Monaghan , Rajendran Krishnasamy , Solomon Mulugeta , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Rajendran Krishnasamy , Solomon Mulugeta , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/37452
摘要： A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.
摘要翻译：在CMOS图像传感器的保持栅晶体管和传输栅极晶体管之间提供一组帧传输晶体管，以便能够在曝光之后存储在感光二极管中产生的电荷。可以在CMOS图像传感器的多次曝光之后，在每个帧转移晶体管中的每个电荷向着传输门晶体管移动之前执行来自该组帧转移晶体管的电荷的读出。启用有用的操作模式，包括用于快速捕获连续图像的突发模式操作和其中以不同曝光时间拍摄多个图像的高动态范围操作，或者通过组合帧传输晶体管的扩散来提供大的电容。

60. 发明授权

US08006211B2 IC chip and design structure including stitched circuitry region boundary identification 有权
标题翻译： IC芯片和设计结构包括缝合电路区域边界识别
公开(公告)号：US08006211B2
公开(公告)日：2011-08-23
申请号：US12112336
申请日：2008-04-30
申请人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
发明人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译：针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。

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