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51. 发明授权

US07466188B2 Stress control mechanism for use in high-voltage applications in an integrated circuit 失效
标题翻译：用于集成电路中高压应用的应力控制机构
公开(公告)号：US07466188B2
公开(公告)日：2008-12-16
申请号：US11614750
申请日：2006-12-21
申请人： John A. Fifield
发明人： John A. Fifield
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H03K17/063 , H03K17/08142 , H03K17/6872 , H03K2217/0027
摘要： A voltage pump circuit that has an oxide stress control mechanism is disclosed. In particular, the oxide stress control mechanism of the voltage pump circuit ensures a safe transistor gate-to-source voltage in high-voltage applications in an integrated circuit. In particular, the down level of the gate voltage of the output transistor may be conditionally limited. For example, an offset in the down level of the gate voltage is created by conditionally developing an offset voltage in the lower rail voltage of the gate driver. The offset voltage is created by directing a predetermined current through a resistance. The current is conditional such that the current is about zero when the power supply voltage is less than or equal to a predetermined level, and the current is greater than zero when the power supply voltage is greater than a predetermined level.
摘要翻译：公开了具有氧化物应力控制机构的电压泵电路。特别地，电压泵电路的氧化物应力控制机构确保在集成电路中的高压应用中的安全的晶体管栅极 - 源极电压。特别地，可以有条件地限制输出晶体管的栅极电压的下降电平。例如，栅极电压的下降电平的偏移是通过有选择地在栅极驱动器的较低轨道电压中产生偏移电压来产生的。通过引导预定电流通过电阻产生偏移电压。电流是有条件的，使得当电源电压小于或等于预定电平时电流约为零，当电源电压大于预定电平时，电流大于零。

52. 发明申请

US20080094896A1 Non Volatile Memory RAD-hard (NVM-rh) System 失效
标题翻译：非易失性存储器RAD-hard（NVM-rh）系统
公开(公告)号：US20080094896A1
公开(公告)日：2008-04-24
申请号：US11550918
申请日：2006-10-19
申请人： Karl R. Erickson , John A. Fifield , Chandrasekara Kothandaraman , Phil C. Paone , William R. Tonti
发明人： Karl R. Erickson , John A. Fifield , Chandrasekara Kothandaraman , Phil C. Paone , William R. Tonti
IPC分类号： G11C17/00 , G11C16/06 , G11C11/34 , G11C16/04
CPC分类号： G11C17/18 , G11C5/005
摘要： The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the component and a sensing circuit coupled to the e-fuse structures. The sensing circuit is adapted to update an external device at a specified time interval to reduce incidence of soft errors and errors due to power failure. Moreover, the sensing circuit is adapted to cease updating the external device to program the e-fuse structures; and, continue updating the external device after programming the e-fuse structures.
摘要翻译：本发明的实施例提供了一种用于非易失性存储器RAD-hard（NVM-rh）系统的装置，方法等。更具体地，IC永久性非易失性存储元件包括集成半导体稳定参考元件，其中该元件对外部辐射具有耐受性。存储元件还包括组件中的e熔丝结构和耦合到电熔丝结构的感测电路。感测电路适于以特定的时间间隔更新外部设备，以减少由于电源故障引起的软错误和错误的发生。此外，感测电路适于停止更新外部设备以编程电熔丝结构; 并且在编程电熔丝结构之后继续更新外部设备。

53. 发明申请

US20080002451A1 SYSTEM AND METHOD FOR DIFFERENTIAL EFUSE SENSING WITHOUT REFERENCE FUSES 有权
标题翻译：没有参考熔丝的差分EFUSE感应系统和方法
公开(公告)号：US20080002451A1
公开(公告)日：2008-01-03
申请号：US11427849
申请日：2006-06-30
申请人： Darren L. Anand , John A. Fifield , Michael R. Ouellette
发明人： Darren L. Anand , John A. Fifield , Michael R. Ouellette
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A differential fuse sensing system includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：差分保险丝感测系统包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到熔丝支脚的第一输入节点和耦合到参考的第二节点的差分读出放大器电压。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

54. 发明授权

US07268577B2 Changing chip function based on fuse states 有权
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US07268577B2
公开(公告)日：2007-09-11
申请号：US11016220
申请日：2004-12-17
申请人： Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
发明人： Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
IPC分类号： H03K19/00
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。操作和/或访问可以基于存储在诸如电可编程熔丝（eFUSES）的非易失性存储元件中的值来提供。

55. 外观设计

USD538448S1 Roof tile 有权
公开(公告)号：USD538448S1
公开(公告)日：2007-03-13
申请号：US29231965
申请日：2005-06-13
申请人： John A. Fifield , William R. Powel
设计人： John A. Fifield , William R. Powel

56. 发明授权

US06917319B1 Digital to analog converter using tunneling current element 失效
标题翻译：使用隧道电流元件的数模转换器
公开(公告)号：US06917319B1
公开(公告)日：2005-07-12
申请号：US10708877
申请日：2004-03-30
申请人： Wagdi W. Abadeer , John A. Fifield
发明人： Wagdi W. Abadeer , John A. Fifield
IPC分类号： H03M1/76 , H03M1/00 , H03M1/66
CPC分类号： H03M1/76
摘要： A method and structure for a digital-to-analog converter comprising a voltage source supply; a voltage division stack connected to the voltage source supply; a multiplexer connected to the voltage division stack; a digital circuit connected to the multiplexer; an analog circuit connected to the multiplexer; and an input binary word source connected to the digital circuit, wherein outputs of the digital circuit are input into the analog circuit and converted as analog output. According to the invention, the multiplexer comprises any of an NFET and/or a PFET. The digital-to-analog converter further comprises a capacitor connected to the analog circuit and a binary-weighted tunneling current device connected to the digital circuit. The multiplexer and the capacitor are made of thick oxide (at least 5 nm thick). The tunneling current device outputs tunneling current, wherein the tunneling current is adjusted in proportion to a binary weight of the input binary word source.
摘要翻译：一种用于数模转换器的方法和结构，包括电压源电源; 连接到电压源电源的分压堆; 连接到电压分组的多路复用器; 连接到多路复用器的数字电路; 连接到多路复用器的模拟电路; 以及连接到数字电路的输入二进制字源，其中数字电路的输出被输入到模拟电路中并转换为模拟输出。根据本发明，多路复用器包括NFET和/或PFET中的任一个。数模转换器还包括连接到模拟电路的电容器和连接到数字电路的二进制加权隧道电流器件。多路复用器和电容器由厚氧化物（至少5nm厚）制成。隧道电流装置输出隧道电流，其中隧道电流与输入二进制字源的二进制权重成比例地调整。

57. 发明授权

US06879638B1 Method and apparatus for providing communication between electronic devices 失效
标题翻译：用于在电子设备之间提供通信的方法和装置
公开(公告)号：US06879638B1
公开(公告)日：2005-04-12
申请号：US09473935
申请日：1999-12-28
申请人： Claude L. Bertin , Anthony R. Bonaccio , John A. Fifield , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , John A. Fifield , Wilbur D. Pricer , William R. Tonti
IPC分类号： H04L25/49 , H04L27/10
CPC分类号： H04L25/4906 , H04L25/4902
摘要： A method and system for providing communication between electronic devices that uses the phase of data transmitted between the devices to indicate logical one and zero values. The method and system has the added benefit of relieving the traditional limitations of voltage communication restraints between devices having differing core voltages (i.e. Differing generations).
摘要翻译：一种用于在电子设备之间提供通信的方法和系统，其使用在设备之间传输的数据的相位来指示逻辑1和零值。该方法和系统具有减轻在具有不同核心电压的器件（即不同代）之间的电压通信约束的传统限制的附加益处。

58. 发明授权

US06577154B2 Constant impedance driver for high speed interface 有权
标题翻译：用于高速接口的恒定阻抗驱动器
公开(公告)号：US06577154B2
公开(公告)日：2003-06-10
申请号：US09848454
申请日：2001-05-03
申请人： John A. Fifield , Russell J. Houghton
发明人： John A. Fifield , Russell J. Houghton
IPC分类号： H03K1716
CPC分类号： H04L25/028 , H03K19/00384 , H04L25/0278
摘要： A compensated driver for maintaining constant impedance during data transfer from an integrated circuit comprises an output portion having an output device to transfer data from the integrated circuit and a mimic circuit portion having a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A mimic circuit portion has a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A differential amplifier portion is adapted to generate a control voltage in response to a reference voltage and the sample voltage. A predrive portion applies either a ground or the predetermined control voltage from the differential amplifier portion to the output stage portion in response to an input, the control voltage regulating the output device in the output stage portion to achieve a more constant impedance.
摘要翻译：用于在从集成电路进行数据传输期间保持恒定阻抗的补偿驱动器包括具有输出装置以从集成电路传送数据的输出部分和具有缩放到适于接受的输出装置的一部分的样本输出装置的模拟电路部分参考电流并产生采样电压。模拟电路部分具有缩放到适于接受参考电流并且产生采样电压的输出设备的一部分的采样输出设备。差分放大器部分适于响应于参考电压和采样电压而产生控制电压。预驱动部分响应于输入将来自差分放大器部分的接地或预定控制电压施加到输出级部分，控制电压调节输出级部分中的输出器件以实现更恒定的阻抗。

59. 发明授权

US06552944B2 Single bitline direct sensing architecture for high speed memory device 有权
标题翻译：用于高速存储器件的单位线直接感测架构
公开(公告)号：US06552944B2
公开(公告)日：2003-04-22
申请号：US09870755
申请日：2001-05-31
申请人： John A. Fifield , Toshiaki Kirihata , Wing K. Luk , Jeremy K. Stephens , Daniel W. Storaska
发明人： John A. Fifield , Toshiaki Kirihata , Wing K. Luk , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G11C702
CPC分类号： G11C7/067 , G11C7/062 , G11C11/4091
摘要： A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area. By accessing the bitline pair individually, two sets of control signals for the pre-charge, EQ0, EQ1, are developed to allow for bitline shielding in the array.
摘要翻译：单个位线直接感测架构采用位于每个存储器阵列中的4晶体管读出放大器电路，其中晶体管用于选择性地将数据位从位线对的真位置或补码位线传送到数据线。数据线优选地布置在多个存储器阵列上。读取和写入操作可能共享或不共享数据行。一个电流源另外用于在读取模式下对数据进行预充电，通过检测电流源和由相应阵列的位线驱动的晶体管之间的电阻比来执行数字感测方案的功能。可以使用简单的逆变器来检测由电阻比确定的数据线的电平。以单端方式检测位线对，消除了对交叉耦合的CMOS器件的需要，从而减少了所需的布局面积。通过单独访问位线对，开发了用于预充电EQ0，EQ1的两组控制信号，以允许阵列中的位线屏蔽。

60. 发明授权

US06496037B1 Automatic off-chip driver adjustment based on load characteristics 有权
标题翻译：基于负载特性的自动片外驱动器调整
公开(公告)号：US06496037B1
公开(公告)日：2002-12-17
申请号：US09588202
申请日：2000-06-06
申请人： Claude L. Bertin , John A. Fifield , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K190175
CPC分类号： H03K19/0005
摘要： An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.
摘要翻译：提供了一种自动驱动器调节器及其使用方法，其基于负载特性修改片外驱动器。优选的实施方案优选是自动的，并且需要很少的或不需要人为干预。本发明的优选实施例分析和确定节点的阻抗并且响应于节点的阻抗调整输出驱动器的数量，或者分析由输入波形引起的节点的合成波形，并且调整多个输出驱动器响应于该结点的合成波形。

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