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51. 发明授权

US06171895B2 Fabrication of buried channel devices with shallow junction depth 失效
标题翻译：具有浅结深度的埋地通道器件的制造
公开(公告)号：US06171895B2
公开(公告)日：2001-01-09
申请号：US09173547
申请日：1998-10-16
申请人： Jih-Wen Chou , Shih-Wei Sun
发明人： Jih-Wen Chou , Shih-Wei Sun
IPC分类号： H01L218238
CPC分类号： H01L29/7838 , H01L21/26513 , H01L21/8238 , H01L21/823807 , H01L27/0927 , H01L29/66477
摘要： The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation of an N-type dopant as an antipunchthrough implant. A junction is formed between the P-type threshold adjust implant and the N-type buried channel stop implant at a relatively shallow depth so that the depth of the buried channel region is limited by the buried channel stop implant, reducing the short channel effect. The channel doping profile is formed so that diffsion of impurities from the channel region to the gate oxide is prevented. The buried channel stop implant is made first through a sacrificial oxide layer. The sacrificial oxide is etched and a gate oxide layer and a thin film of polysilicon are deposited on the surface of the gate oxide. Both the threshold implant and the antipunchthrough implant are made through the thin polysilicon layer and the gate oxide layer. After the channel doping profile is defined, additional gate material is deposited and device construction is completed in the normal manner.
摘要翻译： PMOS场效应晶体管的沟道掺杂分布由P型掺杂剂的浅分布组成，作为阈值调整注入，作为掩埋沟道停止注入的N型掺杂剂的深度分布以及N 型掺杂剂作为抗穿通植入物。在P型阈值调整植入物和N型埋入通道停止植入物之间形成一个相对较浅深度的结，使得掩埋沟道区域的深度受到掩埋沟道阻挡植入物的限制，从而减少短沟道效应。形成通道掺杂分布，从而防止杂质从沟道区域到栅极氧化物的杂化。首先通过牺牲氧化物层制造掩埋沟道阻挡植入物。蚀刻牺牲氧化物，并且栅极氧化物层和多晶硅薄膜沉积在栅极氧化物的表面上。通过薄多晶硅层和栅极氧化物层制造阈值植入和抗穿通植入物两者。在限定沟道掺杂分布之后，沉积额外的栅极材料并以正常方式完成器件结构。

52. 发明授权

US6143601A Method of fabricating DRAM 有权
标题翻译：制造DRAM的方法
公开(公告)号：US6143601A
公开(公告)日：2000-11-07
申请号：US208714
申请日：1998-12-09
申请人： Shih-Wei Sun
发明人： Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/316 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10894 , H01L27/10897 , H01L28/60 , H01L21/31604 , H01L21/76838 , H01L27/10814 , H01L27/10852 , H01L28/91
摘要： A method of fabricating DRAM and embedded DRAM. A contact pad is formed in the periphery/logic circuitry region simultaneously with the formation of the bit line in the memory region. A metal-insulator-metal (MIM) capacitor structure is formed in the memory region by damascene, and a contact and a contact pad are formed in the periphery/logic circuitry region. The formation of the contact in the periphery/logic circuitry is formed step by step to lower the difficulty to fabricate the deep contact. The capacitor electrodes are made by metal layers, which can increase the capacitance of the capacitor.
摘要翻译：一种制造DRAM和嵌入式DRAM的方法。在周边/逻辑电路区域中形成接触焊盘，同时在存储区域中形成位线。金属 - 绝缘体 - 金属（MIM）电容器结构通过镶嵌形成在存储区域中，并且在外围/逻辑电路区域中形成触点和接触焊盘。周边/逻辑电路中接触的形成是逐步形成的，以降低制造深度接触的难度。电容器电极由金属层制成，这可以增加电容器的电容。

53. 发明授权

US5998251A Process and structure for embedded DRAM 失效
标题翻译：嵌入式DRAM的处理和结构
公开(公告)号：US5998251A
公开(公告)日：1999-12-07
申请号：US975492
申请日：1997-11-21
申请人： H. J. Wu , Shih-Wei Sun , Jacob Chen , Tri-Rung Yew
发明人： H. J. Wu , Shih-Wei Sun , Jacob Chen , Tri-Rung Yew
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： An integrated circuit device having both an array of logic circuits and an array of embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions of the logic FETs are subjected to a salicide process at this initial phase and a thick planarized oxide layer is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias are formed to expose each of the source drain regions of the DRAM transfer FETs and to expose select conductors within the logic circuits. A titanium nitride layer is deposited over the device and within the various contact vias through the planarized oxide layer. A capacitor dielectric layer is provided over the device and then the capacitor dielectric layer is selectively removed from at least the contact vias that become bit line contacts and logic interconnects. A layer of tungsten is deposited and patterned to provide upper capacitor electrodes and to complete the bit line contacts and logic interconnects. This first level tungsten layer also can provide bit line wiring. The 1/2 V.sub.cc potential for the upper capacitor electrodes can be provided to the circuit using a level of interconnect wiring also used by the logic circuits.
摘要翻译：使用避免嵌入式DRAM集成的一些最重要的处理挑战的过程来提供具有逻辑电路阵列和嵌入式DRAM电路阵列的集成电路器件。为嵌入式DRAM电路提供转移FET和布线，并且在该过程的初始阶段为器件的逻辑部分提供FET。逻辑FET的栅极电极和源极/漏极区域在该初始阶段经受自对准硅化物处理，并且在嵌入式DRAM区域和逻辑电路区域上均设置厚平坦化的氧化物层。接下来使用常规蚀刻，氮化钛沉积和钨沉积步骤形成电容器和逻辑互连。形成接触通孔以暴露DRAM传输FET的每个源极漏极区域并暴露在逻辑电路内的选择导体。氮化钛层通过平坦化的氧化物层沉积在器件上并在各种接触孔内。在器件上提供电容器介电层，然后至少选择性地从形成位线接触和逻辑互连的接触孔中去除电容器介质层。沉积钨层并图案化以提供上层电容器电极并完成位线接触和逻辑互连。该第一级钨层也可以提供位线布线。上电容器电极的+ E，fra 1/2 + EE Vcc电位可以使用也由逻辑电路使用的互连布线的电平提供给电路。

54. 发明授权

US5496764A Process for forming a semiconductor region adjacent to an insulating layer 失效
标题翻译：用于形成与绝缘层相邻的半导体区域的工艺
公开(公告)号：US5496764A
公开(公告)日：1996-03-05
申请号：US270542
申请日：1994-07-05
申请人： Shih-Wei Sun
发明人： Shih-Wei Sun
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76283 , Y10S148/012 , Y10S148/135
摘要： An insulating layer is formed over a first substrate. Trenches are formed within a second substrate, and those trenches are filled with an insulating layer. The two substrate are bonded at their insulating layers. The portion of the second substrate away from the trenches is removed to form semiconductor regions over the insulating layer of the first substrate. Embodiments of the present invention allow better thickness control for SOI regions and lower leakage current compared to SOI layers that use LOCOS-type field isolation.
摘要翻译：在第一基板上形成绝缘层。沟槽形成在第二基板内，并且那些沟槽被填充绝缘层。两个基板在它们的绝缘层上结合。去除第二衬底远离沟槽的部分，以在第一衬底的绝缘层上形成半导体区域。与使用LOCOS型场隔离的SOI层相比，本发明的实施例允许SOI区域更好的厚度控制和更低的漏电流。

55. 发明授权

US5406111A Protection device for an intergrated circuit and method of formation 失效
标题翻译：集成电路的保护装置和形成方法
公开(公告)号：US5406111A
公开(公告)日：1995-04-11
申请号：US205477
申请日：1994-03-04
申请人： Shih-Wei Sun
发明人： Shih-Wei Sun
IPC分类号： H01L27/02 , H01L29/90 , H01L21/265
CPC分类号： H01L27/0251
摘要： An input/output protection device for an integrated circuit is formed using a trench (22). A first electrode region (46) is formed adjacent a first portion of the trench sidewall (24), and a second electrode region (48) is formed adjacent a second portion of the trench sidewall (24). One of the electrode regions is then electrically coupled to an input/output pad, while the other electrode region is electrically coupled to ground. Excessive voltages on the input/output pad are then discharged when the electrode, which is electrically coupled to the input/output pad, punches through to the electrode that is electrically coupled to ground.
摘要翻译：使用沟槽（22）形成用于集成电路的输入/输出保护装置。在沟槽侧壁（24）的第一部分附近形成第一电极区域（46），并且邻近沟槽侧壁（24）的第二部分形成第二电极区域（48）。然后电极区域中的一个电耦合到输入/输出焊盘，而另一个电极区域电耦合到地。当电耦合到输入/输出焊盘的电极穿过电耦合到地的电极时，输出/输出焊盘上的过大的电压被放电。

56. 发明授权

US07615434B2 CMOS device and fabricating method thereof 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US07615434B2
公开(公告)日：2009-11-10
申请号：US11389617
申请日：2006-03-24
申请人： Shih-Wei Sun , Shih-Fang Tzou , Jiunn-Hsiung Liao , Pei-Yu Chou
发明人： Shih-Wei Sun , Shih-Fang Tzou , Jiunn-Hsiung Liao , Pei-Yu Chou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/7843
摘要： A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the first-type MOS transistor is disposed on the first active area of the substrate, and the second-type MOS transistor is disposed on the second active area of the substrate. The first stress layer is compliantly disposed on the first-type MOS transistor of the first active area. The first liner layer is compliantly disposed on the first stress layer. The second stress layer is compliantly disposed on the second-type MOS transistor of the second active area.
摘要翻译：提供一种CMOS器件，包括衬底，第一类型MOS晶体管，第二类型MOS晶体管，第一应力层，第一衬里层和第二应力层。衬底具有由隔离结构隔开的第一有源区和第二有源区。此外，第一型MOS晶体管设置在衬底的第一有源区上，并且第二型MOS晶体管设置在衬底的第二有源区上。第一应力层顺应地设置在第一有源区的第一型MOS晶体管上。第一衬里层顺应地设置在第一应力层上。第二应力层顺从地设置在第二有源区的第二型MOS晶体管上。

57. 发明授权

US06492732B2 Interconnect structure with air gap compatible with unlanded vias 有权
标题翻译：互连结构与空隙兼容，与非接地通孔
公开(公告)号：US06492732B2
公开(公告)日：2002-12-10
申请号：US09849666
申请日：2001-05-04
申请人： Ellis Lee , Shih-Wei Sun
发明人： Ellis Lee , Shih-Wei Sun
IPC分类号： H01L23522
CPC分类号： H01L21/7682 , H01L21/76802
摘要： An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure. The opening may also expose a top portion of a sidewall of the conductive structure if a misalignment occurs, but the opening does not expose the air gap due to protection from the predetermined distance of the capping layer within the air gap. A next level of conductive structure can be formed to fill the opening. A liner layer can be also formed on a sidewall of the substructure interfacing the air gap, so as to protect the conductive structure.
摘要翻译：互连结构具有其上已经形成有器件的衬底。电介质层覆盖在衬底上。在电介质层上形成具有至少两个由气隙分隔的子结构的导电结构。覆盖层覆盖导电结构和气隙。在气隙上方的一部分上的覆盖层也填充到气隙中预定的距离。气隙也可以延伸到电介质层中以具有更大的高度。在覆盖层上形成蚀刻停止层。在蚀刻停止层上形成金属间介电层。将金属间介电层，蚀刻停止层和覆盖层图案化以形成露出导电结构的顶表面的开口。如果发生不对准，则开口也可能暴露出导电结构的侧壁的顶部部分，但是由于防止气隙内的封盖层的预定距离的保护，开口不暴露气隙。可以形成下一级的导电结构以填充开口。衬垫层也可以形成在与气隙接合的子结构的侧壁上，以便保护导电结构。

58. 发明授权

US06492256B2 Method for forming an interconnect structure with air gap compatible with unlanded vias 有权
标题翻译：用于形成具有与未通孔的空隙兼容的互连结构的方法
公开(公告)号：US06492256B2
公开(公告)日：2002-12-10
申请号：US10098718
申请日：2002-03-15
申请人： Ellis Lee , Shih-Wei Sun
发明人： Ellis Lee , Shih-Wei Sun
IPC分类号： H01L214763
CPC分类号： H01L21/7682 , H01L21/76802
摘要： An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure. The opening may also expose a top portion of a sidewall of the conductive structure if a misalignment occurs, but the opening does not expose the air gap due to protection from the predetermined distance of the capping layer within the air gap. A next level of conductive structure can be formed to fill the opening. A liner layer can be also formed on a sidewall of the substructure interfacing the air gap, so as to protect the conductive structure.
摘要翻译：互连结构具有其上已经形成有器件的衬底。电介质层覆盖在衬底上。在电介质层上形成具有至少两个由气隙隔开的子结构的导电结构。覆盖层覆盖导电结构和气隙。在气隙上方的一部分上的覆盖层也填充到气隙中预定的距离。气隙也可以延伸到电介质层中以具有更大的高度。在覆盖层上形成蚀刻停止层。在蚀刻停止层上形成金属间介电层。将金属间介电层，蚀刻停止层和覆盖层图案化以形成露出导电结构的顶表面的开口。如果发生不对准，则开口也可能暴露出导电结构的侧壁的顶部部分，但是由于防止气隙内的封盖层的预定距离的保护，开口不暴露气隙。可以形成下一级的导电结构以填充开口。衬垫层也可以形成在与气隙接合的子结构的侧壁上，以便保护导电结构。

59. 发明授权

US6153459A Method of fabricating dual gate structure of embedded DRAM 失效
标题翻译：嵌入式DRAM双栅结构的制作方法
公开(公告)号：US6153459A
公开(公告)日：2000-11-28
申请号：US192643
申请日：1998-11-16
申请人： Shih-Wei Sun
发明人： Shih-Wei Sun
IPC分类号： H01L21/8242 , H01L21/8244
CPC分类号： H01L27/10873 , H01L27/10894
摘要： A method of fabricating a dual gate of embedded DRAM forms a conductive layer on a substrate having a memory cell region and a logic circuitry. A gate structure is then formed on the substrate of the memory cell region and the conductive layer of the logic circuitry is removed by patterning the conductive layer. A polysilicon layer is then deposited and a dual gate structure is formed by patterning the polysilicon layer, and simultaneously, a polysilicon spacer is formed on the sidewall of the gate structure in the logic circuitry. The polysilicon spacer is then removed. An insulated spacer is formed on the sidewall of the gate structure and the dual gate structure, and a silicide layer is formed on the dual gate structure and the exposed substrate of the logic circuitry.
摘要翻译：制造嵌入式DRAM的双栅极的方法在具有存储单元区域和逻辑电路的衬底上形成导电层。然后在存储单元区域的衬底上形成栅极结构，并且通过图案化导电层来去除逻辑电路的导电层。然后沉积多晶硅层，并且通过图案化多晶硅层形成双栅极结构，同时，在逻辑电路中的栅极结构的侧壁上形成多晶硅间隔物。然后去除多晶硅间隔物。在栅极结构和双栅极结构的侧壁上形成绝缘间隔物，并且在双栅极结构和逻辑电路的暴露的衬底上形成硅化物层。

60. 发明授权

US6025253A Differential poly-edge oxidation for stable SRAM cells 失效
标题翻译：用于稳定SRAM单元的差分多边缘氧化
公开(公告)号：US6025253A
公开(公告)日：2000-02-15
申请号：US76779
申请日：1998-05-13
申请人： Shih-Wei Sun
发明人： Shih-Wei Sun
IPC分类号： H01L21/8234 , H01L21/8244 , H01L27/11 , H01L29/423 , H01L21/28 , H01L21/336
CPC分类号： H01L21/823456 , H01L27/11 , H01L27/1104 , H01L29/42368 , Y10S257/903 , Y10S257/904
摘要： An SRAM cell having improved stability includes pass transistors having gate electrodes which are shaped by oxidation so that the lower edges of the gate electrodes are raised away from the substrate surface. Because the gate electrodes of the load and pull-down transistors are masked during the oxidation process, the gate electrodes of the load and pull-down transistors have the conventional rectangular shape. The modified shape of the gate electrodes of the pass transistors decreases the current flowing through the pass transistors relative to that which flows through the pull-down transistors, reducing the likelihood that data can inadvertently be lost from the SRAM cell.
摘要翻译：具有改进的稳定性的SRAM单元包括具有通过氧化成形的栅电极的通过晶体管，使得栅电极的下边缘远离基板表面升高。因为负载和下拉晶体管的栅电极在氧化过程中被掩蔽，所以负载和下拉晶体管的栅电极具有常规的矩形形状。传导晶体管的栅电极的修改形状相对于流经下拉晶体管的电流减小了流经通过晶体管的电流，减少了数据可能无意中从SRAM单元丢失的可能性。

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