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51. 发明授权

US07974030B2 Systems and methods for dibit correction 有权
标题翻译：双向校正的系统和方法
公开(公告)号：US07974030B2
公开(公告)日：2011-07-05
申请号：US12463626
申请日：2009-05-11
申请人： George Mathew , Hongwei Song , Yuan Xing Lee
发明人： George Mathew , Hongwei Song , Yuan Xing Lee
IPC分类号： G11B20/10
CPC分类号： G11B20/10203 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for providing a corrected dibit signal. As an example, various embodiments of the present invention provide dibit correction circuits. Such dibit correction circuits include a dibit sample buffer, a maximum sample detector circuit, a side sample detector circuit, and a dibit correction circuit. The dibit sample buffer includes a plurality of samples of an uncorrected dibit signal. The maximum sample detector circuit identifies a maximum sample of the plurality of samples of the uncorrected dibit signal, and the side sample detector circuit identifies a first side sample prior to the maximum sample on the uncorrected dibit signal and a second side sample following the maximum sample on the uncorrected dibit signal. The dibit correction circuit applies a correction factor calculated based at least in part on the maximum sample, the first side sample and the second side sample to at least a subset of the plurality of samples of the uncorrected dibit signals to yield a plurality of corrected dibit signals.
摘要翻译：本发明的各种实施例提供了用于提供校正的双位信号的系统和方法。作为示例，本发明的各种实施例提供双向校正电路。这种二进制校正电路包括二进制采样缓冲器，最大采样检测器电路，侧样本检测器电路和二位校正电路。双位采样缓冲器包括多个未校正的双位信号的样本。最大样本检测器电路识别未校正的双位信号的多个样本的最大样本，并且侧样本检测器电路识别在未校正的双位信号上的最大样本之前的第一侧样本，以及最大样本之后的第二侧样本对未校正的双位信号。双向校正电路将至少部分地基于最大采样，第一侧采样和第二侧采样计算的校正因子应用于未校正的双位信号的多个采样的至少一个子集，以产生多个校正的双位信号。

52. 发明授权

US07859780B2 Systems and methods for on-the-fly write pre-compensation estimation 有权
标题翻译：用于即时写入预补偿估计的系统和方法
公开(公告)号：US07859780B2
公开(公告)日：2010-12-28
申请号：US12199379
申请日：2008-08-27
申请人： George Mathew , Yuan Xing Lee , Hongwei Song
发明人： George Mathew , Yuan Xing Lee , Hongwei Song
IPC分类号： G11B5/09 , G11B5/02
CPC分类号： G11B5/09 , G11B20/10194
摘要： Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide systems for on-the-fly estimation of write pre-compensation values. Such systems include a magnetic storage medium, a read/write head assembly disposed in relation to the magnetic storage medium, and an analog to digital converter that receives an analog signal from the read/write head assembly corresponding to a data set stored on the magnetic storage medium and provides a series of digital samples corresponding to the data set. The storage devices further include a read data processing circuit that receives the same series of digital samples and provides a user data output, and a pre-compensation value calculation circuit that receives the series of digital samples and provides an updated write pre-compensation value.
摘要翻译：本发明的各种实施例提供了用于写入预补偿的系统和方法。例如，本发明的各种实施例提供用于写入预补偿值的即时估计的系统。这样的系统包括磁存储介质，相对于磁存储介质设置的读/写头组件和模数转换器，其从读/写头组件接收对应于存储在磁盘上的数据集的模拟信号并提供与数据集相对应的一系列数字样本。存储装置还包括读取数据处理电路，其接收相同系列的数字样本并提供用户数据输出，以及预补偿值计算电路，其接收一系列数字样本并提供更新的写入预补偿值。

53. 发明申请

US20100185906A1 ERROR CORRECTION CAPABILITY ADJUSTMENT OF LDPC CODES FOR STORAGE DEVICE TESTING 失效
标题翻译：用于存储器件测试的LDPC码的错误校正能力调整
公开(公告)号：US20100185906A1
公开(公告)日：2010-07-22
申请号：US12402359
申请日：2009-03-11
申请人： Richard Rauschmayer , Hongwei Song
发明人： Richard Rauschmayer , Hongwei Song
IPC分类号： G11C29/04 , H03M13/35 , G06F11/10 , G06F11/22
CPC分类号： G11B20/1803 , G11B20/1816 , G11C29/028 , G11C29/42 , G11C2029/0411 , H03M13/1102
摘要： Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.
摘要翻译：本文描述的方法和结构提供了用于调整LDPC纠错码的纠错能力。例如，一个实施例的系统包括适于对已经用LDPC纠错码编码的数据进行解码的解码器。该系统还包括通信地耦合到解码器并且适于在解码器解码之前估计数据中的位值的检测器。检测器还适于基于比特值估计改变比特值，以减少LDPC纠错码的纠错能力。误差校正能力的降低是可调节的，从而可以逐渐分析存储设备的扇区故障率。

54. 发明申请

US20100088357A1 Systems and Methods for Memory Efficient Signal and Noise Estimation 有权
标题翻译：用于存储器高效信号和噪声估计的系统和方法
公开(公告)号：US20100088357A1
公开(公告)日：2010-04-08
申请号：US12247378
申请日：2008-10-08
申请人： George Mathew , Yuan Xing Lee , Hongwei Song , David L. Parker , Scott M. Dziak
发明人： George Mathew , Yuan Xing Lee , Hongwei Song , David L. Parker , Scott M. Dziak
IPC分类号： G06F7/38 , G06F7/50 , G06F7/52
CPC分类号： H04B17/327 , H04B17/26
摘要： Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses a storage medium that includes a Na×Nw data pattern. The Na×Nw data pattern includes Na bits repeated Nw times. Both Na and Nw are each greater than one. The methods further include performing an initial read of the Na×Nw data pattern, which is stored to a first register. Nr subsequent reads of the Na×Nw data pattern are each processed by: performing a subsequent read of the Na×Nw data pattern, and performing a difference calculation using the initial read of the Na×Nw data pattern and the subsequent read of the Na×Nw data pattern and resulting in the calculation of a difference vector that is stored to a second register; and performing a difference accumulation calculation to generate an accumulation vector which is stored to a third register. Based at least in part on the stored Na×Nw data pattern and the stored difference vector, an electronics noise power is calculated.
摘要翻译：本发明的各种实施例提供了用于估计接收信号组中的信号和噪声功率的系统和方法。例如，本发明的一个实施例提供了一种用于确定信号功率和噪声功率的方法。该方法使用包括Na×Nw数据模式的存储介质。 Na×Nw数据模式包括重复N次的Na比特。 Na和Nw都大于1。所述方法还包括执行存储到第一寄存器的Na×Nw数据模式的初始读取。 N×Nw数据模式的后续读取各自通过以下处理：执行Na×Nw数据模式的后续读取，并且使用Na×Nw数据模式的初始读取和随后的Na读数执行差分计算 ×Nw数据模式，并导致存储到第二寄存器的差矢量的计算; 以及执行差积累计算，以产生存储到第三寄存器的累加向量。至少部分地基于存储的Na×Nw数据模式和存储的差分矢量，计算电子噪声功率。

55. 发明申请

US20090276689A1 Using short burst error detector in a queue-based system 有权
标题翻译：在基于队列的系统中使用短脉冲串错误检测器
公开(公告)号：US20090276689A1
公开(公告)日：2009-11-05
申请号：US12380237
申请日：2009-02-25
申请人： Weijun Tan , Shaohua Yang , Hongwei Song
发明人： Weijun Tan , Shaohua Yang , Hongwei Song
IPC分类号： G06F11/07
CPC分类号： H03M13/27 , H03M13/09 , H03M13/1102 , H03M13/15 , H03M13/1515 , H03M13/2957 , H03M13/2987 , H03M13/3746 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6337
摘要： A system, method, and device for detecting short burst errors in a queue-based system is disclosed. A first detector performs a data detection on a first input data set at a first time and on a second input data set at a second time. A second detector performs a data re-detection on input data sets. A decoder decodes derivations of the outputs of the first and second detector. A short burst error detector may perform a short burst error detection on decoded data and erase any detected errors. An output data buffer stores and orders the decoded data for output.
摘要翻译：公开了一种用于检测基于队列的系统中的短脉冲串错误的系统，方法和装置。第一检测器在第一时间对第一输入数据集合和第二输入数据集进行数据检测。第二检测器对输入数据集执行数据重新检测。解码器解码第一和第二检测器的输出的导数。短脉冲串错误检测器可对解码数据执行短脉冲串错误检测，并擦除任何检测到的错误。输出数据缓冲器存储并排序解码数据进行输出。

56. 发明授权

US07421643B2 Data detection and decoding system and a method of detecting and decoding data 失效
标题翻译：数据检测和解码系统以及数据检测和解码方法
公开(公告)号：US07421643B2
公开(公告)日：2008-09-02
申请号：US11029148
申请日：2005-01-04
申请人： Hongwei Song , German Feyh
发明人： Hongwei Song , German Feyh
IPC分类号： H03M13/00
CPC分类号： H04L1/0054 , H03M13/098 , H03M13/29 , H03M13/2909 , H03M13/2933 , H03M13/4146 , H03M13/6343 , H04L1/0063
摘要： A data detection and decoding system in which a single parity bit added to the end of each code word by the encoder is used in the channel detector to improve the accuracy with which bit decisions are made in the channel detector. The bit estimates and the reliability estimates are then processed by the decoder to recover the original input bits. By using single parity for this dual purpose in combination with a decoder that follows the channel detector and uses the bit estimates and reliability estimates to recover the original input bits, performance of the data detection and decoding system is greatly improved while also overcoming the disadvantages of known digital recording systems.
摘要翻译：一种数据检测和解码系统，其中在信道检测器中使用由编码器添加到每个码字的末尾的单个奇偶校验位，以提高在信道检测器中进行位决定的精度。然后由解码器处理比特估计和可靠性估计以恢复原始输入比特。通过将这种双重目的的单一奇偶校验与跟随信道检测器的解码器结合使用，并使用比特估计和可靠性估计来恢复原始输入比特，数据检测和解码系统的性能大大提高，同时克服了已知的数字录音系统。

57. 发明申请

US20070192666A1 Systems and methods for error reduction associated with information transfer 有权
标题翻译：与信息传输相关的错误减少的系统和方法
公开(公告)号：US20070192666A1
公开(公告)日：2007-08-16
申请号：US11341963
申请日：2006-01-26
申请人： Hongwei Song , Weijun Tan
发明人： Hongwei Song , Weijun Tan
IPC分类号： H03M13/00
CPC分类号： H03M13/29 , G11B20/10296 , G11B20/1833 , G11B2020/1836 , H03M13/098 , H03M13/1515 , H03M13/3746 , H03M13/6331
摘要： Various systems and methods for error reduction in a digital information system are disclosed herein. As one example, a digital storage system is provided that includes a storage medium that with an encoded data set accessible via a buffer. The systems further include a soft output Viterbi algorithm channel detector operable to receive the encoded data set, and to provide a hard and a soft output representing the encoded data set. The hard and the soft output from the soft output Viterbi algorithm channel detector are provided to a single parity row decoder that provides another hard output that is an error reduced representation of the encoded data set. The encoded data set is additionally provided from the buffer to another channel detector via a delay element. The delay element time shifts the encoded data set to create a time shifted encoded data set. The hard output from the single parity row decoder and the time shifted encoded data set are provided to coincident with each other to another channel detector. This other channel detector provides a recovered output that exhibits a reduction in errors compared with the encoded data set.
摘要翻译：本文公开了用于数字信息系统中的差错减少的各种系统和方法。作为一个示例，提供数字存储系统，其包括具有经由缓冲器可访问的编码数据集的存储介质。所述系统还包括软输出维特比算法信道检测器，其可操作以接收编码数据集，并提供表示编码数据集的硬和软输出。来自软输出维特比算法信道检测器的硬和软输出被提供给单个奇偶校验行解码器，其提供作为编码数据集的错误减少表示的另一硬输出。编码数据集通过延迟元件从缓冲器附加地提供给另一个通道检测器。延迟元件时间移动编码数据集以创建时移编码数据集。提供来自单个奇偶校验行解码器和时移编码数据组的硬输出以彼此重合到另一个通道检测器。该另一通道检测器提供了与编码数据集相比显示出差错的恢复输出。

58. 发明申请

US20060168493A1 Data detection and decoding system and method 有权
标题翻译：数据检测与解码系统及方法
公开(公告)号：US20060168493A1
公开(公告)日：2006-07-27
申请号：US11041694
申请日：2005-01-24
申请人： Hongwei Song
发明人： Hongwei Song
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G11B20/1803 , G06F11/1008 , H03M13/41 , H03M13/4146 , H03M13/4153 , H03M13/6502
摘要： A data detection and decoding system includes a SOVA channel detector that uses single parity (SOVASP) to improve the accuracy with which the detector estimates bits. Each column or row read back from the read channel constitutes a code word and each code word is encoded to satisfy single parity. Because the SOVASP channel detector detects whether each code word satisfies single parity, it is unnecessary to use both a column decoder and a row decoder in the channel decoder. Either the row decoder or the column decoder can be eliminated depending on whether bits are read back on a column-by-column basis or on a row-by-row basis. This reduction in components reduces hardware complexity and improves system performance. The output of the row or column decoder is received by a second detector that processes the output received from the decoder to recover the original information bits.
摘要翻译：数据检测和解码系统包括使用单个奇偶校验（SOVASP）的SOVA信道检测器来提高检测器估计比特的精度。从读取通道读回的每个列或行构成一个代码字，每个代码字被编码以满足单个奇偶校验。因为SOVASP信道检测器检测每个码字是否满足单个奇偶校验，所以不必在信道解码器中使用列解码器和行解码器。取决于是逐列还是逐行读取位是否可以排除行解码器或列解码器。组件的这种减少降低了硬件复杂性并提高了系统性能。行或列解码器的输出由处理从解码器接收的输出的第二检测器接收以恢复原始信息位。

59. 发明授权

US10302133B2 Sealing structure for bearing 有权
公开(公告)号：US10302133B2
公开(公告)日：2019-05-28
申请号：US15747299
申请日：2016-06-01
申请人： Hongwei Song , Ling Nan , Fuqiang Cai , Uwe Niebling , Zhiheng Liu , Xin Liu
发明人： Hongwei Song , Ling Nan , Fuqiang Cai , Uwe Niebling , Zhiheng Liu , Xin Liu
IPC分类号： F16C33/78 , F16C33/80 , F16C19/36 , F16C19/38
摘要： Bearing sealing structures are disclosed, which may include first and second frameworks configured to attach to an outer ring and an inner ring, respectively, and an elastic sealing member. The first framework may include a first radially extending part extending towards the inner ring, the second framework may include a second radially extending part extending towards the outer ring, and the second radially extending part may be located on an axially outer side of the first radially extending part. The sealing structure may form a first chamber and a second chamber in a radial direction, the first chamber being formed by the first or second radially extending part. The second chamber may be located on a radially inner side of the first chamber, and the elastic sealing member may include a first sealing member extending into the first chamber and a second sealing member extending into the second chamber.

60. 发明授权

US09281908B2 Systems and methods for memory efficient signal and noise estimation 有权
标题翻译：用于存储器高效信号和噪声估计的系统和方法
公开(公告)号：US09281908B2
公开(公告)日：2016-03-08
申请号：US12247378
申请日：2008-10-08
申请人： George Mathew , Yuan Xing Lee , Hongwei Song , David L. Parker , Scott M. Dziak
发明人： George Mathew , Yuan Xing Lee , Hongwei Song , David L. Parker , Scott M. Dziak
IPC分类号： G06F17/10 , H04B17/327 , H04B17/26
CPC分类号： H04B17/327 , H04B17/26
摘要： Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses a storage medium that includes a Na×Nw data pattern. The Na×Nw data pattern includes Na bits repeated Nw times. Both Na and Nw are each greater than one. The methods further include performing an initial read of the Na×Nw data pattern, which is stored to a first register. Nr subsequent reads of the Na×Nw data pattern are each processed by: performing a subsequent read of the Na×Nw data pattern, and performing a difference calculation using the initial read of the Na×Nw data pattern and the subsequent read of the Na×Nw data pattern and resulting in the calculation of a difference vector that is stored to a second register; and performing a difference accumulation calculation to generate an accumulation vector which is stored to a third register. Based at least in part on the stored Na×Nw data pattern and the stored difference vector, an electronics noise power is calculated.
摘要翻译：本发明的各种实施例提供了用于估计接收信号组中的信号和噪声功率的系统和方法。例如，本发明的一个实施例提供了一种用于确定信号功率和噪声功率的方法。该方法使用包括Na×Nw数据模式的存储介质。 Na×Nw数据模式包括重复N次的Na比特。 Na和Nw都大于1。所述方法还包括执行存储到第一寄存器的Na×Nw数据模式的初始读取。 N×Nw数据模式的后续读取各自通过以下处理：执行Na×Nw数据模式的后续读取，并且使用Na×Nw数据模式的初始读取和随后的Na读数执行差分计算 ×Nw数据模式，并导致存储到第二寄存器的差矢量的计算; 以及执行差积累计算，以产生存储到第三寄存器的累加向量。至少部分地基于存储的Na×Nw数据模式和存储的差分矢量，计算电子噪声功率。

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