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51. 发明授权

US08161264B2 Techniques for data prefetching using indirect addressing with offset 有权
标题翻译：使用间接寻址偏移量进行数据预取的技术
公开(公告)号：US08161264B2
公开(公告)日：2012-04-17
申请号：US12024246
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/1045 , G06F2212/6028
摘要： A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch instruction. Content, that is included in a first data block (e.g., a first cache line) of a memory, at the first memory address is then fetched. An offset is then added to the content of the memory at the first memory address to provide a first offset memory address. A second memory address is then determined based on the first offset memory address. A second data block (e.g., a second cache line) that includes data at the second memory address is then fetched (e.g., from the memory or another memory). A data prefetch instruction may be indicated by a unique operational code (opcode), a unique extended opcode, or a field (including one or more bits) in an instruction.
摘要翻译：使用间接寻址执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。然后取出包含在第一存储器地址的存储器的第一数据块（例如，第一高速缓存行）中的内容。然后将偏移量添加到第一存储器地址处的存储器的内容以提供第一偏移存储器地址。然后基于第一偏移存储器地址确定第二存储器地址。包括第二存储器地址上的数据的第二数据块（例如，第二高速缓存行）然后被取出（例如，从存储器或另一个存储器）。数据预取指令可以由指令中的唯一操作代码（操作码），唯一扩展操作码或字段（包括一个或多个位）来指示。

52. 发明申请

US20110296115A1 Assigning Memory to On-Chip Coherence Domains 有权
标题翻译：将内存分配给片上一致性域
公开(公告)号：US20110296115A1
公开(公告)日：2011-12-01
申请号：US12787939
申请日：2010-05-26
申请人： William E. Speight , Lixin Zhang
发明人： William E. Speight , Lixin Zhang
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831
摘要： A mechanism is provided for assigning memory to on-chip cache coherence domains. The mechanism assigns caches within a processing unit to coherence domains. The mechanism then assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller. If a cache line is not found within the coherence domain, the memory controller accesses the memory to retrieve the cache line.
摘要翻译：提供了一种用于将存储器分配给片上高速缓存一致性域的机制。该机制将处理单元内的高速缓存分配给相干域。该机制然后将大块内存分配给一致性域。该机制监视在处理单元内的核心上运行的应用程序，以识别应用程序的需求。然后，该机制可以基于在相干域中运行的应用的需要将存储器块重新分配给高速缓存一致性域。当存储器控制器接收高速缓存未命中时，存储器控制器可以查找映射存储器块到高速缓存一致性域的查找表中的地址。侦听请求被发送到连贯域内的缓存。如果在相干域内的高速缓存中找到高速缓存行，则通过直接或通过存储器控制器的高速缓存行的高速缓存将高速缓存行返回到始发高速缓存。如果在相干域内没有找到高速缓存行，则内存控制器访问内存以检索高速缓存行。

53. 发明申请

US20110296097A1 Mechanisms for Reducing DRAM Power Consumption 失效
标题翻译：降低DRAM功耗的机制
公开(公告)号：US20110296097A1
公开(公告)日：2011-12-01
申请号：US12789019
申请日：2010-05-27
申请人： Elmootazbellah N. Elnozahy , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： Elmootazbellah N. Elnozahy , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G11C11/406 , G11C11/4094 , G11C2211/4065 , G11C2211/4067 , Y02D10/13 , Y02D10/14
摘要： Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells.
摘要翻译：提供用于禁止动态随机存取存储器（DRAM）结构的存储器单元的预充电的机制。这些机制接收到用于访问DRAM结构的存储单元的命令。这些机制基于该命令进一步确定如果禁止在访问存储器单元之后对存储单元进行预充电。此外，机构响应于指示要禁止对存储器单元进行预充电的确定，发送阻止DRAM结构的逻辑以阻止访问存储器单元之后的存储器单元的预充电的命令。

54. 发明申请

US20110292597A1 Stackable Module for Energy-Efficient Computing Systems 有权
标题翻译：用于节能计算系统的可堆叠模块
公开(公告)号：US20110292597A1
公开(公告)日：2011-12-01
申请号：US12789617
申请日：2010-05-28
申请人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
发明人： John B. Carter , Wael R. El-Essawy , Elmootazbellah N. Elnozahy , Wesley M. Felter , Madhusudan K. Iyengar , Thomas W. Keller, JR. , Karthick Rajamani , Juan C. Rubio , William E. Speight , Lixin Zhang
IPC分类号： G06F1/20 , G06F13/00
CPC分类号： H05K7/20 , G06F1/181 , G06F1/20
摘要： A modular processing module is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side in the set of processing module sides couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system.
摘要翻译：提供模块化处理模块。模块化处理模块包括一组处理模块侧面。每个处理模块侧包括电路板，耦合到电路板的多个连接器以及耦合到电路板的多个处理节点。处理模块组中的每个处理模块侧均使用多个连接器中的至少一个连接器耦合到另一个处理模块侧，使得当所有这组处理模块侧面耦合在一起时，形成模块化处理模块。模块化处理模块包括到电源和通信系统的外部连接。

55. 发明授权

US07958316B2 Dynamic adjustment of prefetch stream priority 有权
标题翻译：预取流优先级的动态调整
公开(公告)号：US07958316B2
公开(公告)日：2011-06-07
申请号：US12024411
申请日：2008-02-01
申请人： William E. Speight , Lixin Zhang
发明人： William E. Speight , Lixin Zhang
IPC分类号： G06F12/12 , G06F5/12
CPC分类号： G06F12/0862 , G06F2212/1041 , G06F2212/6024
摘要： A method, processor, and data processing system for dynamically adjusting a prefetch stream priority based on the consumption rate of the data by the processor. The method includes a prefetch engine issuing a prefetch request of a first prefetch stream to fetch one or more data from the memory subsystem. The first prefetch stream has a first assigned priority that determines a relative order for scheduling prefetch requests of the first prefetch stream relative to other prefetch requests of other prefetch streams. Based on the receipt of a processor demand for the data before the data returns to the cache or return of the data along time before the receiving the processor demand, logic of the prefetch engine dynamically changes the first assigned priority to a second higher or lower priority, which priority is subsequently utilized to schedule and issue a next prefetch request of the first prefetch stream.
摘要翻译：一种用于基于处理器的数据的消耗速率动态地调整预取流优先级的方法，处理器和数据处理系统。该方法包括预取引擎，其发出第一预取流的预取请求以从存储器子系统获取一个或多个数据。第一预取流具有第一分配的优先级，其相对于其他预取流的其他预取请求确定第一预取流的调度预取请求的相对顺序。基于在数据返回到高速缓存之前对数据的接收处理器需求，或者在接收到处理器需求之前的时间返回数据，预取引擎的逻辑动态地将第一分配的优先级改变为第二较高或更低的优先级随后利用该优先级来调度和发出第一预取流的下一个预取请求。

56. 发明申请

US20110004875A1 Method and System for Performance Isolation in Virtualized Environments 有权
标题翻译：虚拟化环境下性能隔离的方法与系统
公开(公告)号：US20110004875A1
公开(公告)日：2011-01-06
申请号：US12495842
申请日：2009-07-01
申请人： Elmootazbellah N. Elnozahy , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Elmootazbellah N. Elnozahy , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F9/455 , G06F3/01
CPC分类号： G06F9/50 , G06F9/455 , G06F9/5005 , G06F9/5011 , G06F9/5061 , G06F13/00
摘要： A method, a system, an apparatus, and a computer program product for allocating resources of one or more shared devices to one or more partitions of a virtualization environment within a data processing system. At least one user defined resource assignment is received for one or more devices associated with the data processing system. One or more registers, associated with the one or more partitions are dynamically set to execute the at least one resource assignment, whereby the at least one resource assignment enables a user defined quantitative measure (number and/or percentage) of devices to operate when the one or more transactions are executed via the partition. The system enables the one or more devices to execute one or more transactions at a bandwidth/capacity that is less than or equal to the user defined resource assignment and minimizes performance interference among partitions.
摘要翻译：一种用于将一个或多个共享设备的资源分配给数据处理系统内的虚拟化环境的一个或多个分区的方法，系统，设备和计算机程序产品。为与数据处理系统相关联的一个或多个设备接收至少一个用户定义的资源分配。与所述一个或多个分区相关联的一个或多个寄存器被动态地设置为执行所述至少一个资源分配，由此所述至少一个资源分配使得用户定义的定量测量（数量和/或百分比）能够在设备一个或多个事务通过分区执行。该系统使得一个或多个设备能够以小于或等于用户定义的资源分配的带宽/容量来执行一个或多个事务，并且最小化分区之间的性能干扰。

57. 发明授权

US07783870B2 Branch target address cache 失效
标题翻译：分支目标地址缓存
公开(公告)号：US07783870B2
公开(公告)日：2010-08-24
申请号：US11837893
申请日：2007-08-13
申请人： David S. Levitan , William E. Speight , Lixin Zhang
发明人： David S. Levitan , William E. Speight , Lixin Zhang
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address. The branch logic accesses the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first processor clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a later second processor clock cycle.
摘要翻译：处理器包括执行单元和从存储器系统执行指令的指令排序逻辑。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括一级分支目标地址高速缓存（BTAC）和二级BTAC，每级具有相应的多个条目，每个条目将至少一个标签与预测的分支目标地址相关联。分支逻辑与第一指令获取地址的标签部分并行地访问一级和二级BTAC以从第一级BTAC获得第一预测分支目标地址，以在第一处理器时钟周期中用作第二指令获取地址以及来自第二级BTAC的第二预测分支目标地址，以在随后的第二处理器时钟周期中用作第三指令提取地址。

58. 发明申请

US20090198948A1 Techniques for Data Prefetching Using Indirect Addressing 有权
标题翻译：使用间接寻址的数据预取技术
公开(公告)号：US20090198948A1
公开(公告)日：2009-08-06
申请号：US12024186
申请日：2008-02-01
申请人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A technique for performing indirect data prefetching includes determining a first memory address of a pointer associated with a data prefetch instruction. Content of a memory at the first memory address is then fetched. A second memory address is determined from the content of the memory at the first memory address. Finally, a data block (e.g., a cache line) including data at the second memory address is fetched (e.g., from the memory or another memory).
摘要翻译：用于执行间接数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。然后获取第一个存储器地址上的存储器的内容。从第一存储器地址处的存储器的内容确定第二存储器地址。最后，取出包括第二存储器地址上的数据的数据块（例如，高速缓存行）（例如，从存储器或另一个存储器）。

59. 发明申请

US20090132767A1 COMPLIER ASSISTED VICTIM CACHE BYPASSING 失效
标题翻译：合作协助VICTIM CACHE BYPASSING
公开(公告)号：US20090132767A1
公开(公告)日：2009-05-21
申请号：US12355019
申请日：2009-01-16
申请人： Yaoqing Gao , William E. Speight , Lixin Zhang
发明人： Yaoqing Gao , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/127 , Y02D10/13
摘要： A method for compiler assisted victim cache bypassing including: identifying a cache line as a candidate for victim cache bypassing; conveying a bypassing-the-victim-cache information to a hardware; and checking a state of the cache line to determine a modified state of the cache line, wherein the cache line is identified for cache bypassing if the cache line that has no reuse within a loop or loop nest and there is no immediate loop reuse or there is a substantial across loop reuse distance so that it will be replaced from both main and victim cache before being reused.
摘要翻译：一种用于编译器辅助的受害者缓存旁路的方法，包括：将高速缓存行标识为用于受害者缓存旁路的候选者; 向硬件传送绕过受害者缓存信息; 并且检查高速缓存行的状态以确定高速缓存行的修改状态，其中如果在循环或循环嵌套内没有重用的高速缓存行并且不存在立即循环重用或那里，则高速缓存行被识别用于高速缓存绕过是一个实质的跨循环重用距离，因此它将被重新使用之前被替换为主缓存和受害缓存。

60. 发明申请

US20090113164A1 Method, System and Program Product for Address Translation Through an Intermediate Address Space 有权
标题翻译：通过中间地址空间进行地址转换的方法，系统和程序产品
公开(公告)号：US20090113164A1
公开(公告)日：2009-04-30
申请号：US11928125
申请日：2007-10-30
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F9/26
CPC分类号： G06F12/1063 , G06F12/1072
摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.
摘要翻译：在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。使用中间地址访问高速缓冲存储器。响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。使用实际地址访问系统内存。

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