专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20060244080A1 Profile confinement to improve transistor performance 有权
公开(公告)号：US20060244080A1
公开(公告)日：2006-11-02
申请号：US11114567
申请日：2005-04-25
申请人： Chien-Hao Chen , Chun-Feng Nieh , Karen Mai , Tze-Liang Lee
发明人： Chien-Hao Chen , Chun-Feng Nieh , Karen Mai , Tze-Liang Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7843 , H01L21/26506 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/6659
摘要： A semiconductor device having well-defined profiles is disclosed. A p-type pocket/halo region is preferably formed along a channel-side border of the heavily doped source/drain region to neutralize diffused n-type elements. A diffusion-retarding region is formed to retard diffusion for both p-type and n-type impurities by substantially overlapping or extending beyond the p-type pocket/halo region and the N+ S/D region at least on the channel side.

52. 发明授权

US07935587B2 Advanced forming method and structure of local mechanical strained transistor 有权
标题翻译：局部机械应变晶体管的先进成形方法和结构
公开(公告)号：US07935587B2
公开(公告)日：2011-05-03
申请号：US11450210
申请日：2006-06-09
申请人： Chien-Hao Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/28123 , H01L21/823807 , H01L27/0922 , H01L29/16 , H01L29/161 , H01L29/7833
摘要： Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.
摘要翻译：本发明的实施例提供半导体制造方法和应变晶体管的结构。一种方法包括在MOS晶体管上形成应力层。在栅电极上选择性地蚀刻应力层，从而影响MOSFET沟道区内的应变条件。 NMOS晶体管可以具有拉伸应力层，并且PMOS晶体管可以具有压应力层。

53. 发明授权

US07498642B2 Profile confinement to improve transistor performance 有权
标题翻译：简介限制提高晶体管性能
公开(公告)号：US07498642B2
公开(公告)日：2009-03-03
申请号：US11114567
申请日：2005-04-25
申请人： Chien-Hao Chen , Chun-Feng Nieh , Karen Mai , Tze-Liang Lee
发明人： Chien-Hao Chen , Chun-Feng Nieh , Karen Mai , Tze-Liang Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7843 , H01L21/26506 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/6659
摘要： A semiconductor device having well-defined profiles is disclosed. A p-type pocket/halo region is preferably formed along a channel-side border of the heavily doped source/drain region to neutralize diffused n-type elements. A diffusion-retarding region is formed to retard diffusion for both p-type and n-type impurities by substantially overlapping or extending beyond the p-type pocket/halo region and the N+ S/D region at least on the channel side.
摘要翻译：公开了具有明确定义的轮廓的半导体器件。优选地，在重掺杂源极/漏极区域的沟道侧边界处形成p型口/晕区域以中和扩散的n型元件。形成扩散阻滞区域以通过至少在通道侧基本上重叠或延伸超过p型口/晕区域和N + S / D区域来延迟p型和n型杂质两者的扩散。

54. 发明申请

US20060263992A1 Method of forming the N-MOS and P-MOS gates of a CMOS semiconductor device 审中-公开
标题翻译：形成CMOS半导体器件的N-MOS和P-MOS栅极的方法
公开(公告)号：US20060263992A1
公开(公告)日：2006-11-23
申请号：US11133967
申请日：2005-05-20
申请人： Chien-Hao Chen , Chun-Feng Nieh , Karen Mai , Tze-Liang Lee
发明人： Chien-Hao Chen , Chun-Feng Nieh , Karen Mai , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/28035 , H01L21/32155 , H01L21/823842
摘要： A method for forming the N-MOS and P-MOS transistor regions of a CMOS device having reduced depletion of the N and P dopants in the polysilicon gate and reduced penetration of the N and P dopants through the oxide layer and into the channel regions of the N-MOS and the P-MOS transistor. The improvements are accomplished by a new implantation treatment of the polysilicon gate layer prior to implanting the polysilicon layer with the N-type dopant and the P-type dopant for purposes of forming the transistor gates. The implantation treatment prior to the N-type dopant and P-type dopant implantation, includes a first implantation of Ge and/or an inert gas and a second implantation of carbon or fluorine.
摘要翻译：一种用于形成CMOS器件的N-MOS和P-MOS晶体管区域的方法，其具有减少多晶硅栅极中的N和P掺杂剂的耗尽并且减少了N和P掺杂剂穿过氧化物层并渗透到沟道区域 N-MOS和P-MOS晶体管。为了形成晶体管栅极的目的，在将N型掺杂剂和P型掺杂剂注入多晶硅层之前，通过对多晶硅栅极层的新的注入处理来实现改进。在N型掺杂剂和P型掺杂剂注入之前的注入处理包括Ge和/或惰性气体的第一注入和碳或氟的第二次注入。

55. 发明申请

US20060234455A1 Structures and methods for forming a locally strained transistor 审中-公开
标题翻译：用于形成局部应变晶体管的结构和方法
公开(公告)号：US20060234455A1
公开(公告)日：2006-10-19
申请号：US11109279
申请日：2005-04-19
申请人： Chien-Hao Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Tze-Liang Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L29/165 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： Embodiments of the invention provide structures and methods for forming a strained MOS transistor. A preferred embodiment includes creating a compressive strain in a PMOS transistor for improving carrier mobility without the need for source/drain recess formation and SiGe epitaxy. Embodiments comprise forming a gate electrode on a silicon substrate, and forming a lightly doped source/drain (LDS/LDD) region in the substrate by simultaneously implanting germanium and boron in the substrate using the gate electrode as a mask. Embodiments further comprise forming spacers on opposite sidewalls of the gate electrode and forming a heavily doped source/drain region in the substrate by simultaneously implanting germanium and boron using the gate electrode and the spacers as a mask. Embodiments may further include annealing the semiconductor device to recrystallize SiGe.
摘要翻译：本发明的实施例提供了用于形成应变MOS晶体管的结构和方法。优选实施例包括在PMOS晶体管中产生压缩应变以改善载流子迁移率，而不需要源/漏凹陷形成和SiGe外延。实施例包括在硅衬底上形成栅电极，并且通过使用栅极电极作为掩模，在衬底中同时注入锗和硼，从而在衬底中形成轻掺杂的源极/漏极（LDS / LDD）区域。实施例还包括在栅电极的相对侧壁上形成间隔物，并通过使用栅极电极和间隔物作为掩模同时注入锗和硼，从而在衬底中形成重掺杂的源/漏区。实施例还可以包括退火半导体器件以重结晶SiGe。

56. 发明授权

US08933503B2 Advanced forming method and structure of local mechanical strained transistor 有权
标题翻译：局部机械应变晶体管的先进成形方法和结构
公开(公告)号：US08933503B2
公开(公告)日：2015-01-13
申请号：US13077641
申请日：2011-03-31
申请人： Chien-Hao Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Tze-Liang Lee
IPC分类号： H01L21/8238 , H01L29/78
CPC分类号： H01L29/7843 , H01L21/28123 , H01L21/823807 , H01L27/0922 , H01L29/16 , H01L29/161 , H01L29/7833
摘要： Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.
摘要翻译：本发明的实施例提供半导体制造方法和应变晶体管的结构。一种方法包括在MOS晶体管上形成应力层。在栅电极上选择性地蚀刻应力层，从而影响MOSFET沟道区内的应变条件。 NMOS晶体管可以具有拉伸应力层，并且PMOS晶体管可以具有压应力层。

57. 发明申请

US20080290420A1 SiGe or SiC layer on STI sidewalls 审中-公开
标题翻译： SiGe或SiC层
公开(公告)号：US20080290420A1
公开(公告)日：2008-11-27
申请号：US11805894
申请日：2007-05-25
申请人： Ming-Hua Yu , Tai-Chun Huang , Chien-Hao Chen , Keh-Chiang Ku , Jr.-Hung Li , Ling-Yen Yeh , Tze-Liang Lee
发明人： Ming-Hua Yu , Tai-Chun Huang , Chien-Hao Chen , Keh-Chiang Ku , Jr.-Hung Li , Ling-Yen Yeh , Tze-Liang Lee
IPC分类号： H01L27/092 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7846
摘要： A semiconductor structure includes a semiconductor substrate; an opening in the semiconductor substrate; a semiconductor layer in the opening and covering a bottom and sidewalls of the opening, wherein the semiconductor layer and the semiconductor substrate comprise different materials; and a dielectric material over the semiconductor layer and filling a remaining portion of the opening.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底中的开口; 所述开口中的半导体层覆盖所述开口的底部和侧壁，其中所述半导体层和所述半导体衬底包括不同的材料; 以及在所述半导体层上方的电介质材料，并填充所述开口的剩余部分。

58. 发明申请

US20070298557A1 Junction leakage reduction in SiGe process by tilt implantation 审中-公开
标题翻译：通过倾斜植入在SiGe工艺中的结漏电减少
公开(公告)号：US20070298557A1
公开(公告)日：2007-12-27
申请号：US11607326
申请日：2006-12-01
申请人： Chun-Feng Nieh , Keh-Chiang Ku , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee
发明人： Chun-Feng Nieh , Keh-Chiang Ku , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee
IPC分类号： H01L21/8234
CPC分类号： H01L29/1083 , H01L21/26586 , H01L29/165 , H01L29/6653 , H01L29/7834 , H01L29/7848
摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a stressor in the semiconductor substrate adjacent to an edge of the gate electrode; and tilt implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.
摘要翻译：提供一种形成半导体器件的方法。该方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 在所述半导体衬底中形成与所述栅电极的边缘相邻的应力源; 并且在形成应力器的步骤之后倾斜注入杂质。杂质优选选自基本上由IV族元素，惰性元素及其组合组成的组。

59. 发明申请

US20060246672A1 Method of forming a locally strained transistor 有权
标题翻译：形成局部应变晶体管的方法
公开(公告)号：US20060246672A1
公开(公告)日：2006-11-02
申请号：US11119522
申请日：2005-04-29
申请人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee
发明人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee
IPC分类号： H01L21/336 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/78 , H01L29/7843
摘要： A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.
摘要翻译：本发明的优选实施例提供半导体制造方法。一个实施例包括形成具有侧壁间隔物的MOS器件。高应力层沉积在器件上。在栅极电极和侧壁间隔物上的层的该部分中选择性地调节应力。优选地，栅极上方和侧壁间隔物上的应力层从第一应力调整到第二应力，其中第一应力是拉伸和压缩之一，第二应力是拉伸和压缩中的另一个。优选实施例在PMOS和NMOS沟道区域内选择性地诱发适当的应力，以改善它们各自的载流子迁移率。本发明的其它实施例包括具有上覆应力层的场效应晶体管（FET），所述应力层由不同的应力区域组成。

60. 发明申请

US20070037326A1 Shallow source/drain regions for CMOS transistors 审中-公开
标题翻译： CMOS晶体管的浅源极/漏极区域
公开(公告)号：US20070037326A1
公开(公告)日：2007-02-15
申请号：US11200374
申请日：2005-08-09
申请人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee
发明人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee
IPC分类号： H01L21/84
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/6659 , H01L29/66772 , H01L29/7833
摘要： A transistor having shallow, high-dopant concentration source/drain regions is provided. A gate electrode is formed on a substrate, and the source/drain regions of the substrate are transformed into an amorphous state by, for example, implanting Si, Ge, Xe, In, Ar, Kr, Rn, a combination thereof, or the like ions. A co-implantation process is performed to implant ions of C, N, F, a combination thereof, or the like in the source/drain regions. Thereafter, one or more implants may be performed to form the LDD and source/drain regions and the substrate is recrystallized. The amorphous regions and the co-implantation regions effectively confine or reduce the diffusion of the ions used to form the LDD and source/drain regions.
摘要翻译：提供具有浅掺杂浓度源/漏区的晶体管。在基板上形成栅电极，通过例如注入Si，Ge，Xe，In，Ar，Kr，Rn及其组合，将基板的源极/漏极区域变换为非晶态，或像离子。执行共注入工艺以在源极/漏极区域中注入C，N，F，它们的组合等的离子。此后，可以执行一个或多个植入物以形成LDD和源极/漏极区域，并且衬底被重结晶。非晶区域和共注入区域有效地限制或减少用于形成LDD和源极/漏极区域的离子的扩散。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式