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51. 发明授权

US08910355B2 Method of manufacturing a film bulk acoustic resonator with a loading element 有权
标题翻译：制造具有加载元件的薄膜体声波谐振器的方法
公开(公告)号：US08910355B2
公开(公告)日：2014-12-16
申请号：US13323285
申请日：2011-12-12
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H03H3/04 , H03H9/15 , H03H9/10 , H03H3/02 , H03H3/007 , C23C16/40
CPC分类号： H03H3/04 , C23C16/401 , C23C16/402 , H03H3/007 , H03H3/02 , H03H9/1007 , H03H9/105 , H03H9/1085 , H03H9/1092 , H03H9/173 , H03H2003/021 , H03H2003/0428 , Y10T29/42 , Y10T29/49005 , Y10T29/49126 , Y10T29/49155
摘要： Manufacturing a semiconductor structure including modifying a frequency of a Film Bulk Acoustic Resonator (FBAR) device though a vent hole of a sealing layer surrounding the FBAR device.
摘要翻译：制造半导体结构，包括通过围绕FBAR器件的密封层的通气孔来修改膜体声波谐振器（FBAR）器件的频率。

52. 发明申请

US20130015744A1 SAW FILTER HAVING PLANAR BARRIER LAYER AND METHOD OF MAKING 有权
标题翻译：具有平面屏障层的SAW滤波器及其制造方法
公开(公告)号：US20130015744A1
公开(公告)日：2013-01-17
申请号：US13183977
申请日：2011-07-15
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H01L41/04 , H04R17/00
CPC分类号： H03H9/14538 , H03H3/08
摘要： Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.
摘要翻译：本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片; 设置在所述压电基板上方的平面阻挡层，以及埋设在所述压电基板和所述平面阻挡层中的至少一个导体。

53. 发明授权

US08232190B2 Three dimensional vertical E-fuse structures and methods of manufacturing the same 失效
标题翻译：三维垂直E熔丝结构及其制造方法
公开(公告)号：US08232190B2
公开(公告)日：2012-07-31
申请号：US11865079
申请日：2007-10-01
申请人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
发明人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.
摘要翻译：本文提供三维垂直电子熔丝结构及其制造方法。形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。垂直e熔丝结构包括第一接触层和第二接触层。该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。当施加电流时，导电材料具有增加的电阻。

54. 发明授权

US09543356B2 Pixel sensor cell including light shield 有权
标题翻译：像素传感器单元包括遮光罩
公开(公告)号：US09543356B2
公开(公告)日：2017-01-10
申请号：US12538194
申请日：2009-08-10
申请人： Jeffrey P. Gambino , Mark D. Jaffe , John Ellis-Monaghan , Richard Rassel
发明人： Jeffrey P. Gambino , Mark D. Jaffe , John Ellis-Monaghan , Richard Rassel
IPC分类号： H01L27/148 , H01L27/146
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14623 , H01L27/1464
摘要： CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.
摘要翻译： CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背侧照明的光屏蔽像素传感器单元。在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽遮光层。在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器来代替浮动扩散，并且被定位在载体衬底上的介电隔离金属化堆叠中。

55. 发明授权

US08796130B2 Diffusion barrier for oppositely doped portions of gate conductor 有权
标题翻译：栅极导体相对掺杂部分的扩散势垒
公开(公告)号：US08796130B2
公开(公告)日：2014-08-05
申请号：US13352851
申请日：2012-01-18
申请人： Jeffrey P. Gambino , Russell T. Herrin , Mark D. Jaffe , Laura J. Schutz
发明人： Jeffrey P. Gambino , Russell T. Herrin , Mark D. Jaffe , Laura J. Schutz
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28052
摘要： A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.
摘要翻译：一种在两个紧邻的相反极性的晶体管器件上形成多晶硅栅极的方法。该方法在多晶硅栅极上形成掩模。掩模在相反极性晶体管器件彼此邻接的位置处具有开口。然后，该方法通过开口去除多晶硅栅极的一些（一部分），以在多晶硅栅极中形成至少一个部分凹槽（或潜在的完整开口）。凹槽将多晶硅栅极分离成第一多晶硅栅极和第二多晶硅栅极。在形成凹槽之后，该方法使用第一极性掺杂剂掺杂第一多晶硅栅极，并使用具有与第一极性掺杂剂相反极性的第二极性掺杂剂掺杂第二多晶硅栅极。

56. 发明授权

US08729664B2 Discontinuous guard ring 有权
标题翻译：不连续的护环
公开(公告)号：US08729664B2
公开(公告)日：2014-05-20
申请号：US13437273
申请日：2012-04-02
申请人： Jeffrey P. Gambino , Mark D. Jaffe , Mark D. Levy , John C. Malinowski
发明人： Jeffrey P. Gambino , Mark D. Jaffe , Mark D. Levy , John C. Malinowski
IPC分类号： H01L29/15 , H01L23/52 , H01L29/47 , H01L27/095
CPC分类号： H01L29/0619 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.
摘要翻译：一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并从所述半导体衬底延伸穿过多个布线层中的一个或多个。保护环包括堆叠金属线，空间分开各个金属线。每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。

57. 发明授权

US08723392B2 Saw filter having planar barrier layer and method of making 有权
标题翻译：具有平面阻挡层的锯片和制造方法
公开(公告)号：US08723392B2
公开(公告)日：2014-05-13
申请号：US13183977
申请日：2011-07-15
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H03H9/25
CPC分类号： H03H9/14538 , H03H3/08
摘要： Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.
摘要翻译：本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片; 设置在所述压电基板上方的平面阻挡层，以及埋设在所述压电基板和所述平面阻挡层中的至少一个导体。

58. 发明申请

US20130181293A1 DIFFUSION BARRIER FOR OPPOSITELY DOPED PORTIONS OF GATE CONDUCTOR 有权
标题翻译：用于门式导体的对位部分的扩散障碍物
公开(公告)号：US20130181293A1
公开(公告)日：2013-07-18
申请号：US13352851
申请日：2012-01-18
申请人： Jeffrey P. Gambino , Russell T. Herrin , Mark D. Jaffe , Laura J. Schutz
发明人： Jeffrey P. Gambino , Russell T. Herrin , Mark D. Jaffe , Laura J. Schutz
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28052
摘要： A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.
摘要翻译：一种在两个紧邻的相反极性的晶体管器件上形成多晶硅栅极的方法。该方法在多晶硅栅极上形成掩模。掩模在相反极性晶体管器件彼此邻接的位置处具有开口。然后，该方法通过开口去除多晶硅栅极的一些（一部分），以在多晶硅栅极中形成至少一个部分凹槽（或潜在的完整开口）。凹槽将多晶硅栅极分离成第一多晶硅栅极和第二多晶硅栅极。在形成凹槽之后，该方法使用第一极性掺杂剂掺杂第一多晶硅栅极，并使用具有与第一极性掺杂剂相反极性的第二极性掺杂剂掺杂第二多晶硅栅极。

59. 发明申请

US20130026646A1 PASSIVATED THROUGH WAFER VIAS IN LOW-DOPED SEMICONDUCTOR SUBSTRATES 有权
标题翻译：通过低压半导体衬底中的波形钝化
公开(公告)号：US20130026646A1
公开(公告)日：2013-01-31
申请号：US13193991
申请日：2011-07-29
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Alvin J. Joseph
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Alvin J. Joseph
IPC分类号： H01L21/28 , G06F17/50 , H01L23/48 , H01L21/22 , H01L21/265
CPC分类号： H01L21/76898 , H01L21/26586 , H01L29/732
摘要： A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.
摘要翻译：用于形成钝化的晶片通孔的方法，通过晶片通孔结构钝化，并通过设计结构钝化通过晶片。该方法包括：在半导体衬底中形成贯穿晶片通孔，所述贯通晶片通孔包括从半导体衬底的顶部延伸到半导体衬底的底表面的电导体; 并且形成邻接电导体的所有侧壁的掺杂层，与半导体衬底相同的掺杂剂类型的掺杂层，掺杂层中掺杂剂的浓度大于半导体衬底中掺杂剂的浓度，掺杂层介于电导体和半导体衬底。

60. 发明授权

US09099982B2 Method of manufacturing switching filters and design structures 有权
标题翻译：开关滤波器和设计结构的制造方法
公开(公告)号：US09099982B2
公开(公告)日：2015-08-04
申请号：US13358172
申请日：2012-01-25
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H03H3/08 , H01L41/08 , H03H9/64 , H03H3/007 , H03H9/02
CPC分类号： H03H9/13 , G06F17/5081 , H01L41/08 , H03H3/08 , H03H9/02543 , H03H9/64 , H03H9/6403 , H03H9/6413 , H03H2003/0071 , H03H2009/02299 , Y10T29/42 , Y10T29/49005 , Y10T29/49126 , Y10T29/49147 , Y10T29/49155
摘要： Switchable and/or tunable filters, methods of manufacture and design structures are provided herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode.
摘要翻译：本发明提供了可切换和/或可调滤波器，制造方法和设计结构。形成滤波器的方法包括形成至少一个包括形成在压电基片上的多个电极的压电滤波器结构。该方法还包括在压电基片上形成多个指状物的固定电极。该方法还包括在压电衬底上形成具有多个指状物的可移动电极。该方法还包括形成与可移动电极的多个指状物中的一个或多个对准的致动器。

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