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51. 发明授权

US08455939B2 Stacked metal fin cell 有权
标题翻译：堆叠的金属细胞
公开(公告)号：US08455939B2
公开(公告)日：2013-06-04
申请号：US12974235
申请日：2010-12-21
申请人： Johann Alsmeier , Vinod Purayath , James Kai , George Matamis
发明人： Johann Alsmeier , Vinod Purayath , James Kai , George Matamis
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates located over the channel and a plurality of electrically conducting fins. Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates. Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins.
摘要翻译：一种NAND器件，包括源极，漏极和位于源极和漏极之间的沟道。 NAND器件还包括位于通道上方的多个浮动栅极和多个导电鳍片。多个导电翅片中的每一个位于多个浮动栅极之一上。多个导电翅片包括多晶硅以外的材料。 NAND器件还包括多个控制栅极。多个控制栅极中的每一个位于与多个浮动栅极和多个导电散热片中的每一个相邻的位置。

52. 发明授权

US08946803B2 Method of forming a floating gate with a wide base and a narrow stem 有权
标题翻译：用宽底座和窄杆形成浮动门的方法
公开(公告)号：US08946803B2
公开(公告)日：2015-02-03
申请号：US11951998
申请日：2007-12-06
申请人： George Matamis , Henry Chien , Vinod Robert Purayath , Takashi Whitney Orimoto , James Kai
发明人： George Matamis , Henry Chien , Vinod Robert Purayath , Takashi Whitney Orimoto , James Kai
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L27/108 , H01L29/423
CPC分类号： H01L21/28273 , H01L27/10844 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.
摘要翻译：浮动栅极存储器阵列的浮动栅极在位线方向和字线方向都具有倒T形。使用分离形成浮动栅极的两个多晶硅层的蚀刻停止层形成浮动栅极。字线在一个示例中在浮动栅极上延伸，并且在另一示例中，字线在浮动栅极之间延伸。

53. 发明申请

US20120001252A1 ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF 有权
公开(公告)号：US20120001252A1
公开(公告)日：2012-01-05
申请号：US12827947
申请日：2010-06-30
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L27/115 , H01L21/8246 , H01L21/8247 , H01L29/788 , H01L21/336
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

54. 发明授权

US08330208B2 Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof 有权
标题翻译：超高密度单片三维垂直NAND串存储器件及其制造方法
公开(公告)号：US08330208B2
公开(公告)日：2012-12-11
申请号：US13451009
申请日：2012-04-19
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

55. 发明申请

US20110309430A1 Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation 有权
标题翻译：具有扁平单元结构和空气间隙隔离的非易失性存储器
公开(公告)号：US20110309430A1
公开(公告)日：2011-12-22
申请号：US13162550
申请日：2011-06-16
申请人： Vinod Robert Purayath , George Matamis , Henry Chien , James Kai , Yuan Zhang
发明人： Vinod Robert Purayath , George Matamis , Henry Chien , James Kai , Yuan Zhang
IPC分类号： H01L29/788 , H01L21/764
CPC分类号： H01L27/11524 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L21/7682 , H01L27/11521 , H01L27/11568 , H01L29/0649
摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.
摘要翻译：高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

56. 发明授权

US08946048B2 Method of fabricating non-volatile memory with flat cell structures and air gap isolation 有权
标题翻译：制造具有扁平电池结构和气隙隔离的非易失性存储器的方法
公开(公告)号：US08946048B2
公开(公告)日：2015-02-03
申请号：US13162550
申请日：2011-06-16
申请人： Vinod Robert Purayath , George Matamis , Henry Chien , James Kai , Yuan Zhang
发明人： Vinod Robert Purayath , George Matamis , Henry Chien , James Kai , Yuan Zhang
IPC分类号： H01L21/76
CPC分类号： H01L27/11524 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L21/7682 , H01L27/11521 , H01L27/11568 , H01L29/0649
摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.
摘要翻译：高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

57. 发明授权

US08187936B2 Ultrahigh density vertical NAND memory device and method of making thereof 有权
标题翻译：超高密度垂直NAND存储器件及其制造方法
公开(公告)号：US08187936B2
公开(公告)日：2012-05-29
申请号：US12827947
申请日：2010-06-30
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： A method of making a monolithic three dimensional NAND string. The method includes forming a stack of alternating layers of a first material and a second material over a substrate. The first material includes a conductive or semiconductor control gate material and the second material includes an insulating material. The method also includes etching the stack to form at least one opening in the stack, selectively etching the first material to form first recesses in the first material and forming a blocking dielectric in the first recesses. The method also includes forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric, forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening and forming a semiconductor channel in the at least one opening.
摘要翻译：制造单片三维NAND串的方法。该方法包括在衬底上形成第一材料和第二材料的交替层的叠层。第一材料包括导电或半导体控制栅极材料，第二材料包括绝缘材料。该方法还包括蚀刻堆叠以在堆叠中形成至少一个开口，选择性地蚀刻第一材料以在第一材料中形成第一凹槽并在第一凹槽中形成阻挡电介质。该方法还包括在隔离电介质上的第一凹槽中形成彼此分开的多个离散的电荷存储段，在暴露在至少一个开口中的离散电荷存储段的侧壁上形成隧道电介质，并形成半导体通道在至少一个开口中。

58. 发明申请

US20090147576A1 FLOATING GATE WITH UNIVERSAL ETCH STOP LAYER 有权
标题翻译：浮动门与通用灭火层
公开(公告)号：US20090147576A1
公开(公告)日：2009-06-11
申请号：US11951998
申请日：2007-12-06
申请人： George Matamis , Henry Chien , Vinod Robert Purayath , Takashi Whitney Orimoto , James Kai
发明人： George Matamis , Henry Chien , Vinod Robert Purayath , Takashi Whitney Orimoto , James Kai
IPC分类号： G11C16/04 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/10844 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.
摘要翻译：浮动栅极存储器阵列的浮动栅极在位线方向和字线方向都具有倒T形。使用分离形成浮动栅极的两个多晶硅层的蚀刻停止层形成浮动栅极。字线在一个示例中在浮动栅极上延伸，并且在另一示例中，字线在浮动栅极之间延伸。

59. 发明申请

US20110310653A1 Memory Cell With Resistance-Switching Layers 有权
标题翻译：具有电阻切换层的存储单元
公开(公告)号：US20110310653A1
公开(公告)日：2011-12-22
申请号：US13157191
申请日：2011-06-09
申请人： Franz Kreupl , Xiying Costa , James Kai , Raghuveer S. Makala
发明人： Franz Kreupl , Xiying Costa , James Kai , Raghuveer S. Makala
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

60. 发明授权

US07279410B1 Method for forming inlaid structures for IC interconnections 有权
标题翻译：用于形成IC互连的镶嵌结构的方法
公开(公告)号：US07279410B1
公开(公告)日：2007-10-09
申请号：US10379757
申请日：2003-03-05
申请人： Lynne A. Okada , Fei Wang , James Kai
发明人： Lynne A. Okada , Fei Wang , James Kai
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/311
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76829
摘要： A method for forming an inlaid interconnect structure for ICs. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a dielectric layer and cap layer over the etch stop layer, forming a photoresist pattern, and etching the cap and dielectric to form an opening that is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The dielectric layer and cap layers are then deposited over both regions and two via or trench openings are formed therethrough in the regions, respectively. The first and second etch stop layers protect the underlying substrate from experiencing punchthrough during the via or trench formation. The etch stop layers are then removed in the openings and a conductive material is formed therein.
摘要翻译：一种用于形成用于IC的镶嵌互连结构的方法。该方法包括形成蚀刻停止层，在IC管芯上打开蚀刻停止层的一部分，在蚀刻停止层上形成介电层和覆盖层，形成光致抗蚀剂图案，以及蚀刻帽和电介质以形成开口然后用导电材料（例如金属）填充。该方法还可以包括在蚀刻停止层的开口内形成阻挡层。根据本发明的另一方面，在衬底上形成第一和第二蚀刻停止层，并且将第二蚀刻停止层图案化以限定两个区域，其中具有第一和第二蚀刻停止层的第二区域经历更快的蚀刻速率比第一个地区。然后将介电层和盖层沉积在两个区域上，并且分别在区域中形成两个通孔或沟槽开口。第一和第二蚀刻停止层在通孔或沟槽形成期间保护下面的衬底不经历穿透。然后在开口中去除蚀刻停止层，并在其中形成导电材料。

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