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51. 发明申请

US20070034908A1 Phase change random access memory device 有权
标题翻译：相变随机存取存储器件
公开(公告)号：US20070034908A1
公开(公告)日：2007-02-15
申请号：US11317292
申请日：2005-12-27
申请人： Woo-yeong Cho , Jong-soo Seo , Ik-chul Kim , Young-kug Moon
发明人： Woo-yeong Cho , Jong-soo Seo , Ik-chul Kim , Young-kug Moon
IPC分类号： H01L29/80
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , H01L27/2409 , H01L27/2436
摘要： A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.
摘要翻译：相变随机存取存储器件包括连接到写电路和读电路的全局位线; 多个局部位线，每个位线连接到多个相变存储器单元; 以及选择性地将全局位线与多个局部位线中的每一个连接的多个列选择晶体管。每个列选择晶体管具有取决于与写入电路和读取电路的距离的电阻。

52. 发明授权

US07920405B2 Circuits and methods for adaptive write bias driving of resistive non-volatile memory devices 失效
标题翻译：电阻性非易失性存储器件的自适应写入偏置驱动的电路和方法
公开(公告)号：US07920405B2
公开(公告)日：2011-04-05
申请号：US11957756
申请日：2007-12-17
申请人： Sang-beom Kang , Woo-yeong Cho , Hyung-rok Oh , Joon-min Park
发明人： Sang-beom Kang , Woo-yeong Cho , Hyung-rok Oh , Joon-min Park
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C13/0064 , B82Y10/00 , G11C11/15 , G11C13/0004 , G11C13/0014 , G11C13/0069 , G11C2013/0066 , G11C2013/009 , G11C2013/0092 , G11C2213/79
摘要： A non-volatile memory device includes a memory cell array including a memory cell array having word lines, bit lines, and non-volatile memory cells, each non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line. The variable resistive material has a resistance level that varies according to data to be stored. A selection circuit selects at least one non-volatile memory cell in which data will be written. An adaptive write circuit/method supplies a write bias to the selected non-volatile memory cell through the bit line connected to the selected non-volatile memory cell to write data in the selected non-volatile memory cell and varies (e.g., increases) the write bias until the resistance level of the selected non-volatile memory cell varies.
摘要翻译：非易失性存储器件包括存储单元阵列，其包括具有字线，位线和非易失性存储器单元的存储单元阵列，每个非易失性存储单元具有可变电阻材料和连接在相应字之间的存取元件线和相应的位线。可变电阻材料具有根据要存储的数据而变化的电阻电平。选择电路选择要写入数据的至少一个非易失性存储单元。自适应写入电路/方法通过连接到所选择的非易失性存储器单元的位线向所选择的非易失性存储器单元提供写入偏置，以将数据写入所选择的非易失性存储单元中并且改变（例如，增加）写入偏置，直到所选择的非易失性存储单元的电阻水平变化。

53. 发明授权

US07869256B2 Bi-directional resistive random access memory capable of multi-decoding and method of writing data thereto 有权
标题翻译：能够进行多重解码的双向电阻随机存取存储器及其数据写入方法
公开(公告)号：US07869256B2
公开(公告)日：2011-01-11
申请号：US11957812
申请日：2007-12-17
申请人： Joon-min Park , Sang-beom Kang , Woo-yeong Cho , Hyung-rok Oh
发明人： Joon-min Park , Sang-beom Kang , Woo-yeong Cho , Hyung-rok Oh
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C13/00 , G11C8/08 , G11C13/0028 , G11C13/0069 , G11C2013/009
摘要： A non-volatile memory device is employed in which data values are determined by the polarities at both ends of a cell, The non-volatile memory device includes a first decoder which decodes a plurality of predetermined bit values of a row address into a first address and is disposed in a row direction of a memory cell array; a second decoder which decodes the other bit values of the row address into a second address and is disposed in a column direction of the memory cell array; and a driver which applies bias voltages to a word line which corresponds to the first address or the second address in accordance with the data values. By including first and second decoders and decoding a row address in two steps, a bi-directional RRAM according to the present invention can perform addressing at high speeds while reducing chip size.
摘要翻译：使用非易失性存储器件，其中数据值由单元两端的极性确定。非易失性存储器件包括将行地址的多个预定位值解码为第一地址的第一解码器并且设置在存储单元阵列的行方向上; 第二解码器，其将所述行地址的其他位值解码为第二地址，并且被布置在所述存储单元阵列的列方向上; 以及根据数据值对与第一地址或第二地址对应的字线施加偏置电压的驱动器。通过包括第一和第二解码器并以两个步骤对行地址进行解码，根据本发明的双向RRAM可以在降低芯片尺寸的同时以高速执行寻址。

54. 发明申请

US20100320433A1 Variable Resistance Memory Device and Method of Manufacturing the Same 有权
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US20100320433A1
公开(公告)日：2010-12-23
申请号：US12872876
申请日：2010-08-31
申请人： Yu-hwan Ro , Byung-gil Choi , Woo-yeong Cho , Hyung-rok Oh
发明人： Yu-hwan Ro , Byung-gil Choi , Woo-yeong Cho , Hyung-rok Oh
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： G11C5/063 , G11C13/00 , G11C13/0004 , G11C2213/72 , H01L27/24 , Y10S977/754
摘要： A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.
摘要翻译：一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线形成在全局位线上，均匀分离，并沿第一方向延伸。

55. 发明授权

US07817465B2 Phase change random access memory 有权
标题翻译：相变随机存取存储器
公开(公告)号：US07817465B2
公开(公告)日：2010-10-19
申请号：US12453420
申请日：2009-05-11
申请人： Hyung-rok Oh , Woo-yeong Cho , Beak-hyung Cho
发明人： Hyung-rok Oh , Woo-yeong Cho , Beak-hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A phase change random access (PRAM) memory may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.
摘要翻译：相位随机存取（PRAM）存储器可以包括具有多个相变存储器单元的存储单元阵列和包括补偿单元和读出放大器的数据读取电路，该补偿单元被配置为向感测节点提供补偿电流以补偿由流过多个相变存储器单元之一的电流引起的感测节点的电平的降低，以及被配置为将感测节点的电平与参考电平进行比较并输出结果的读出放大器的比较。

56. 发明授权

US07633100B2 Phase change random access memory device 有权
标题翻译：相变随机存取存储器件
公开(公告)号：US07633100B2
公开(公告)日：2009-12-15
申请号：US11317292
申请日：2005-12-27
申请人： Woo-yeong Cho , Jong-soo Seo , Ik-chul Kim , Young-kug Moon
发明人： Woo-yeong Cho , Jong-soo Seo , Ik-chul Kim , Young-kug Moon
IPC分类号： H01L29/80
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , H01L27/2409 , H01L27/2436
摘要： A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.
摘要翻译：相变随机存取存储器件包括连接到写电路和读电路的全局位线; 多个局部位线，每个位线连接到多个相变存储器单元; 以及选择性地将全局位线与多个局部位线中的每一个连接的多个列选择晶体管。每个列选择晶体管具有取决于与写入电路和读取电路的距离的电阻。

57. 发明授权

US07586776B2 Nonvolatile memory devices having multi-filament variable resistivity memory cells therein 失效
标题翻译：在其中具有多重可变电阻率存储单元的非易失性存储器件
公开(公告)号：US07586776B2
公开(公告)日：2009-09-08
申请号：US11945420
申请日：2007-11-27
申请人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho
发明人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2013/0088 , G11C2013/009 , G11C2013/0092 , G11C2213/31 , G11C2213/32 , G11C2213/79
摘要： There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and the corresponding bit line and an access element; selecting circuits selecting one of the plurality of resistive memory cells; and a filament-forming circuit supplying a filament-forming voltage to the selected resistive memory cell through the bit line coupled to the selected resistive memory cell while increasing the filament-forming voltage from a predetermined voltage level until filaments having a predetermined thickness are formed in the variable resistive material of the selected resistive memory cell.
摘要翻译：提供了一种电阻式存储器件，该器件包括：多个字线和多个位线，其布置成使得字线与位线相交; 每个具有耦合在对应的字线和对应的位线之间的可变电阻材料的电阻性存储单元和一个存取元件; 选择所述多个电阻性存储单元之一的选择电路; 以及丝线形成电路，其通过耦合到所选择的电阻性存储单元的位线向所选择的电阻性存储单元提供丝状形成电压，同时从预定电压电平增加灯丝形成电压，直到形成具有预定厚度的灯丝所选择的电阻性存储单元的可变电阻材料。

58. 发明申请

US20090059658A1 MEMORY SYSTEM, MEMORY DEVICE AND APPARATUS INCLUDING WRITING DRIVER CIRCUIT FOR A VARIABLE RESISTIVE MEMORY 有权
标题翻译：存储器系统，存储器件和设备，包括用于可变电阻存储器的写入驱动器电路
公开(公告)号：US20090059658A1
公开(公告)日：2009-03-05
申请号：US11949299
申请日：2007-12-03
申请人： Beak-hyung Cho , Woo-yeong Cho , Hyung-rok Oh
发明人： Beak-hyung Cho , Woo-yeong Cho , Hyung-rok Oh
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1096 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.
摘要翻译：一种装置，非易失性存储装置和非易失性存储器系统包括易失性可变电阻存储器（VRM）单元阵列和具有脉冲选择电路，电流控制电路和电流驱动电路的写入驱动器电路。电流控制电路接收偏置电压，当数据处于第一电平时，在复位脉冲的使能持续时间期间以第二电平输出控制信号，并且在该组的使能持续时间期间输出处于第一电平的控制信号数据处于第二级时的脉冲。当前驱动电路在复位脉冲或设定脉冲的使能期间内向相变存储器阵列输出写入电流。写入驱动器电路可以根据数据的逻辑电平选择复位脉冲或设置脉冲，并根据复位脉冲或设定脉冲控制施加到相变存储器阵列的电流电平。

59. 发明申请

US20080089105A1 Variable Resistance Memory Device and Method of Manufacturing the Same 有权
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US20080089105A1
公开(公告)日：2008-04-17
申请号：US11865491
申请日：2007-10-01
申请人： Yu-hwan Ro , Byung-gil Choi , Woo-yeong Cho , Hyung-rok Oh
发明人： Yu-hwan Ro , Byung-gil Choi , Woo-yeong Cho , Hyung-rok Oh
IPC分类号： G11C5/06 , H01L21/82
CPC分类号： G11C5/063 , G11C13/00 , G11C13/0004 , G11C2213/72 , H01L27/24 , Y10S977/754
摘要： A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.
摘要翻译：一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线形成在全局位线上，均匀分离，并沿第一方向延伸。

60. 发明申请

US20050068804A1 Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range 有权
标题翻译：相变存储器件和方法，其将相变材料的电阻维持在恒定电阻范围内的复位状态
公开(公告)号：US20050068804A1
公开(公告)日：2005-03-31
申请号：US10937943
申请日：2004-09-11
申请人： Byung-gil Choi , Woo-yeong Cho , Hyung-rok Oh , Beak-hyung Cho
发明人： Byung-gil Choi , Woo-yeong Cho , Hyung-rok Oh , Beak-hyung Cho
IPC分类号： G11C13/00 , G11C13/02 , G11C16/02 , G11C16/34 , H01L27/105 , H01L45/00 , G11C11/00
CPC分类号： G11C13/0004 , G11C13/0064 , G11C13/0069
摘要： Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a reset state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.
摘要翻译：提供了一种相变存储器件和方法，其将相变材料的电阻保持在恒定电阻范围内的复位状态。在该方法中，将数据提供给第一相变存储器单元，然后首先确定存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据是否相同。如果存储在第一相变存储器单元中的数据和提供给第一相变存储单元的数据不相同，则向第一相变存储单元提供互补写入电流，并且第二确定数据存储在第一相变存储单元中，提供给第一相变存储单元的数据相同。如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据相同，则将数据提供给第二相变存储单元。

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