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51. 发明专利

JPH044674A SYNCHRONIZING SEPARATOR CIRCUIT AND DC RESTORATION CIRCUIT USING THE SAME 失效
公开(公告)号：JPH044674A
公开(公告)日：1992-01-09
申请号：JP10541690
申请日：1990-04-23
申请人： HITACHI LTD
发明人： NAKA KAZUTAKA , TAKAHASHI HIROAKI , FURUHATA TAKASHI
IPC分类号： H04N5/08 , H04N5/18
摘要： PURPOSE:To operate the title circuit stably without malfunction even against a level fluctuation of an input video signal and a rapid DC fluctuation by deciding a synchronizing separation level from both a maximum value and a minimum value of the input video signal and comparing the obtained synchronization separation level with the input video signal level and separating synchronizing signal from the input video signal. CONSTITUTION:A video signal whose noise is eliminated by a low pass filter 3 is given to a maximum value latch circuit 4, in which a maximum value signal VMAX representing the maximum value of the video signal is detected and latched. Similarly, the video signal whose noise is eliminated by the low pass filter 3 is given to a minimum value latch circuit 5, in which a minimum value signal VMIN representing the minimum value of the video signal is detected and latched. The detected maximum value signal VMAX minimum value signal VMIN are inputted to a synchronizing separation level generating circuit 6, in which a synchronizing separation level VTH is generated. The synchronizing separation level VTH and the input video signal VL whose noise eliminated by the low pass filter 3 are compared to realize the synchronizing separator circuit with less malfunction due to fluctuation even when a level fluctuation of an input video signal or a rapid DC fluctuation takes place.

52. 发明专利

JPH01129585A VIDEO SIGNAL RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH01129585A
公开(公告)日：1989-05-22
申请号：JP28731087
申请日：1987-11-16
申请人： HITACHI LTD
发明人： TAKAHASHI HIROAKI , FURUHATA TAKASHI , HAMAGUCHI MASAKAZU , HOSOKAWA KYOICHI , NAKA KAZUTAKA
IPC分类号： H04N5/92 , H04N5/7826
摘要： PURPOSE:To realize high-reliability signal processing which is stable against disturbance such as a dropout by inserting a negative-polarity signal in the same shape which indicates the head of a segment in one or plural horizontal scanning periods positioned at the head part of each segment. CONSTITUTION:A memory 102 is read sequentially with an address signal from a read address circuit signal 121, and the read signal is passed through a circuit 107 and converted by a D/A converting circuit 103 into an analog signal ; and a negative V signal is outputted at the two head lines of each segment and then a video signal is outputted it 137 following lines. Consequently, the V signal of 8 lines and the video signal of 548 lines in total are outputted in one vertical scanning period consisting of four segments. Thus, the V signal is provided and then the V signal is securely detected by an integral detection system using a low-pass filter at the time of reproduction; and the head of each track is detected with high reliability and signal processing such as synchronous detection, protection, etc., by tracks is securely performed.

53. 发明专利

JP2000206931A IMAGE DISPLAY DEVICE 失效
公开(公告)号：JP2000206931A
公开(公告)日：2000-07-28
申请号：JP2842699
申请日：1999-02-05
申请人： HITACHI LTD
发明人： NAKA KAZUTAKA , OSAWA MICHITAKA , KONOUE AKIHIKO , OTAKA HIROSHI
IPC分类号： G09G3/20 , G09G3/28
摘要： PROBLEM TO BE SOLVED: To perform a high quality moving image display excellent in a dynam-ic resolution characteristics and making color blotting in a dynamic edge part inconspicuous by allocating a sub-field of the largest light emission weight among plural sub-fields to a central vicinity of one field and switch-ing light emission at a prescribed period. SOLUTION: In the sub-field constitution, the sub-fields SF2, SF5 of the light emission weight 12 and the sub-field SF2, SF6 of the light emission weight 6 are arranged symmetrically around the sub-field SF4 of the largest light emission weight 18. In such a manner, when the sub-fields of the equal light emission weight (SF3, SF5 and SF2, SF6) are arranged symmetrical-ly, even when control of light emission/non-light emission are switched, the same gradation is displayed. Further, by switching the light emission weight arrangement at the period of field, line, pixel, etc., the periodicity of the light emission is randomized further, and a pseudo outline distur-bance is reduced.

54. 发明专利

JP2000206930A IMAGE DISPLAY DEVICE 失效
公开(公告)号：JP2000206930A
公开(公告)日：2000-07-28
申请号：JP2842599
申请日：1999-02-05
申请人： HITACHI LTD
发明人： NAKA KAZUTAKA , OSAWA MICHITAKA , KONOUE AKIHIKO , OTAKA HIROSHI
IPC分类号： G09G3/20 , G09G3/28
摘要： PROBLEM TO BE SOLVED: To perform a high quality moving image display excellent in a dynamic resolution characteristics and making color blotting in a dynamic edge part inconspicuous by allocating a sub-field of the largest weight among plural sub- fields to a central vicinity of one field and light emitting at least one of high- order sub-fields even in any gradation of continuous two or more gradations. SOLUTION: The sub-field SF4 of the largest light emission weight (emitted light quantity) is arranged in the central vicinity of one field, and a chevron light emission distribution so that the light emission weight becomes successively low according to going away from the center to back/forth is adopted. For instance, the light emission weight of 1, 4, 16, 64, 128, 32, 8, 2 are allocated respectively to eight sub-fields SF0, SF1, SF2... SF7 from a top of one field. Then, at least one of high-order sub-fields is light-emitted even in any gradation of continuous two or more gradations. Thus, the switch of the light emission is dispersed without centralizing to the specified gradation.

55. 发明专利

JPH11119730A VIDEO DISPLAY DEVICE 失效
公开(公告)号：JPH11119730A
公开(公告)日：1999-04-30
申请号：JP28712797
申请日：1997-10-20
申请人： HITACHI LTD
发明人： ARAI HIDEO , OKU MASUO , MIZOZOE HIROKI , SUZUKI KEIZO , OSAWA MICHITAKA , KONOUE AKIHIKO , NAKA KAZUTAKA
IPC分类号： G09G3/20 , G09G3/28
摘要： PROBLEM TO BE SOLVED: To reduce a pseudo contour and to decrease a black level without deteriorating gradation, in the expression of gradation by a sub-field method. SOLUTION: A digital video signal DV1 from an A/D conversion means 2 is supplied to a sub-field conversion means 6 through a field storage means 5, with each field divided into plural sub-fields and converted into a sub-field configuration. A matrix display device 9 is driven by the video signal converted to this sub-field configuration. Meantime, the digital video signal DV1 from the A/D conversion means 2 is supplied to a statistical means 3, with the luminance distribution (e.g. maximum luminance level) M detected for each field. A means 4 for deciding a sub-field emission period controls the sub-field conversion means 6, making the sub-field configuration in each field of the digital video signal DV2 correspond to the luminance distribution M, and constituting a configuration that reduces a pseudo contour or a black level.

56. 发明专利

JPH11109916A COLOR PICTURE DISPLAY DEVICE 失效
公开(公告)号：JPH11109916A
公开(公告)日：1999-04-23
申请号：JP28805197
申请日：1997-10-03
申请人： HITACHI LTD
发明人： NAKA KAZUTAKA , OSAWA MICHITAKA , KONOUE AKIHIKO , OTAKA HIROSHI
IPC分类号： G09G3/20 , G09G3/28 , H01J11/22 , H01J11/34 , H01J11/42 , H01J17/04
摘要： PROBLEM TO BE SOLVED: To provide a color picture display device superior in motion resolution characteristic, inconspicuous in color blotting in motion edge part and capable of displaying high quality dynamic picture. SOLUTION: In this device that displays a color picture by supplying color video signals of red, green and blue to each light emitting cell of these colors, assuming time response characteristic of each light emission of these cells to be TR, TG and TB, the difference between TR and TG is made sufficiently small compared with the difference between TR and TB as well as between TG and TB. In addition, as the luminous weight array of the subfield, the one with the largest weight is arranged near the center of one field, with a chevron shaped luminous distribution employed in which the luminous weight becomes successively smaller in the direction away from the center to the front/ rear. otherwise, as the luminous weight array of the subfield having two luminous peaks in one field, the time interval between the two peaks is set at one half field.

57. 发明专利

JPH1152911A MATRIX PANEL DISPLAY DEVICE 失效
公开(公告)号：JPH1152911A
公开(公告)日：1999-02-26
申请号：JP21287997
申请日：1997-08-07
申请人： HITACHI LTD
发明人： KONOUE AKIHIKO , SUZUKI KEIZO , OSAWA MICHITAKA , NAKA KAZUTAKA , OKU MASUO , ARAI HIDEO , MIZOZOE HIROKI
IPC分类号： G09G3/20 , G09G3/28 , G09G3/291 , G09G3/294 , G09G3/296
摘要： PROBLEM TO BE SOLVED: To enable compensating pseudo contour having no feeling of incompatibility even if the line of sight of an observer does not follow movement of a picture and to improve picture quality for animation by adding or subtracting a pseudo contour compensation signal to/from a picture signal only for fast movement. SOLUTION: A value of centroid is obtained with a pixel unit from picture signals of field memories 103, 104 with, a value of difference of centroid between a preceding field and a succeeding field is compared with the reference signal by a comparing circuit 109, when magnitude of difference of centroid is larger than the reference signal, a pseudo contour compensation signal generating circuit 110 is operated. When it is smaller, a value of 0 is outputted from the pseudo contour compensation signal generating circuit 110. A compensation signal is added or subtracted to/from a picture signal from a field memory 104 being a picture signal of the succeeding field by an adding/subtracting circuit 112, stored in a field memory 113, read out by a read-out circuit 114 with timing being adjusted to a display time of a display device, and sent to a display device 117 as a picture signal output 115.

58. 发明专利

JPH1011009A PROCESSOR FOR VIDEO SIGNAL AND DISPLAY DEVICE USING THE SAME 失效
公开(公告)号：JPH1011009A
公开(公告)日：1998-01-16
申请号：JP19433796
申请日：1996-07-24
申请人： HITACHI LTD
发明人： NAKA KAZUTAKA , MARUYAMA ATSUSHI , URATA HIROYUKI
IPC分类号： G09G3/36 , G06T3/40 , G09G3/20 , G09G5/00 , G09G5/18 , G09G5/36 , H04N1/409 , H04N5/66
摘要： PROBLEM TO BE SOLVED: To eliminate the need for a high-speed signal processing circuit and obtain a pixel number converting function of superior picture quality by performing an interpolating process by an arithmetic process between vertical lines through a digital signal process and an interpolating process between horizontal dots through an analog signal process using a low-pass filter. SOLUTION: With a control signal from a readout control circuit 109, data in a memory 106 are converted in the number of lines by a line interpolating circuit 108 through an interpolating arithmetic process from an adjacent line. The data which have been converted in the number of lines are converted by a D/A converting circuit 110 into an analog signal. The low-pass filter 111 removes unnecessary high-frequency components and outputs an output video signal SO from a terminal 112. Further, a display device outputs it from a terminal 115 together with a necessary dot clock. Then the interpolating process by the arithmetic process between vertical lines is performed through the digital process and the interpolating process between horizontal dots is performed through the analog signal process of the low-pass filter 111.

59. 发明专利

JPH09244611A VIDEO SIGNAL PROCESSOR AND DISPLAY DEVICE USING THE SAME 失效
公开(公告)号：JPH09244611A
公开(公告)日：1997-09-19
申请号：JP5131896
申请日：1996-03-08
申请人： HITACHI LTD
发明人： NAKA KAZUTAKA , URATA HIROYUKI , MARUYAMA ATSUSHI , YAMAMOTO KIYOSHI , HIBARA AKIRA
IPC分类号： H04N5/46 , G06F3/14 , G09G1/16 , G09G5/00 , G09G5/12 , G09G5/18 , H04N5/073 , H04N5/12 , H04N5/74 , H04N9/12
摘要： PROBLEM TO BE SOLVED: To facilitate a phase synchronization which is stabilized with respect to only a vertical frequency by resetting a line frequency divider circuit by a reference vertical synchronizing signal. SOLUTION: The N-fold frequency of a reference horizontal synchronizing signal RH to be inputted from terminals 11 is outputted from a VOC 3 as a read clock by a PLL loop consisting of a phase frequency comparator 2, the VOC 3 and a frequency divider circuit 7. An output horizontal synchronizing signal HO is generated by frequency-dividing this read dot clock with the number of a horizontal total dots D including a blanking period by a frequency divider circuit 4 and moreover an output vertical synchronizing signal VO is generated by frequency-dividing this output horizontal synchronizing signal HO with the number of total lines L by a frequency divider circuit 5. Then, the reference vertical synchronizing signal RV inputted from the terminals 11 is inputted to the frequency divider circuit 5 to become constitution resetting the counter in the inside of the frequency divider circuit. Thus, this line frequency divider circuit is made to operate so that the phase of the output vertical synchronizing circuit becomes always same to the reference vertical synchronizing signal RV.

60. 发明专利

JPH0946619A VIDEO SIGNAL PROCESSOR AND DISPLAY SYSTEM 失效
公开(公告)号：JPH0946619A
公开(公告)日：1997-02-14
申请号：JP19209795
申请日：1995-07-27
申请人： HITACHI LTD
发明人： NAKA KAZUTAKA , MARUYAMA ATSUSHI , URATA HIROYUKI , IWANAGA MASAO
IPC分类号： G06F1/10 , G09G5/18 , H03L7/081 , H03L7/091 , H03L7/199 , H04N5/04 , H04N5/12 , H04N5/20 , H04N5/66 , H04N9/64
摘要： PROBLEM TO BE SOLVED: To automatically adjust the sampling phase to an optimum value in the case of A/D-converting a video signal. SOLUTION: An input video signal VO representing a black/white level two- gradation test pattern is converted into 8-bit data at an A/D converter 4 synchronously with a sampling clock generated by a write control circuit 5 and the converted data are stored in a memory 6. An MPU 9 reads data of picture elements for a valid period of a video signal stored in the memory 6, calculates a difference AT between a mean value of white level picture element data larger than a prescribed value and a mean value of black level picture element data smaller than a prescribed value a sum VT between a variance of the white level picture element data and a variance of the black level picture element data and controls a phase of the sampling clock generated by the write control circuit 5 so as to maximize the AT and to minimize the VT.

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