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51. 发明授权

US06667507B2 Flash memory having memory section and peripheral circuit section 失效
标题翻译：具有存储器部分和外围电路部分的闪存
公开(公告)号：US06667507B2
公开(公告)日：2003-12-23
申请号：US09899155
申请日：2001-07-06
申请人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
发明人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.
摘要翻译：半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。

52. 发明授权

US08270220B2 Nonvolatile semiconductor storage device and method for controlling the same 失效
标题翻译：非易失性半导体存储装置及其控制方法
公开(公告)号：US08270220B2
公开(公告)日：2012-09-18
申请号：US12729626
申请日：2010-03-23
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/28 , H01L27/11519 , H01L27/11521
摘要： A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.
摘要翻译：非易失性半导体存储装置包括存储单元阵列和外围电路。存储单元阵列包括沿第一方向延伸的有效区域，在第一方向上延伸的虚拟有源区域，多个有效区域上的存储单元，虚拟有效区域上的第一虚设单元，各自连接到对应存储器的扩散层区域单元和对应的第一虚拟单元，在相应的有效区域中首先接触，并且在虚拟活动区域中的第二触点。外围电路包括电压施加单元，其被配置为向每个第一触点施加第一电压，以将每个存储单元设置在写使能状态或第二电压以将存储单元设置在写禁止状态，并且应用向第二接触器施加第三电压以改变虚设电池的阈值。

53. 发明申请

US20120037976A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20120037976A1
公开(公告)日：2012-02-16
申请号：US13235948
申请日：2011-09-19
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L27/105
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在每个存储单元晶体管，低压晶体管和高压晶体管的源极和漏极区域上的衬垫绝缘膜。

54. 发明授权

US07983086B2 NAND flash memory 失效
标题翻译： NAND闪存
公开(公告)号：US07983086B2
公开(公告)日：2011-07-19
申请号：US12564598
申请日：2009-09-22
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： G11C16/00
CPC分类号： G11C11/5628 , G11C16/0483
摘要： In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor.
摘要翻译：在第一和第二选择栅极晶体管被截止并且第一电压被施加到第二存储单元晶体管的控制栅极的状态下，第二存储单元晶体管连接到从存储器中选择的第一存储单元晶体管的源极线侧单元晶体管并且要被切断，高于第一电压的第二电压并且使得在存储单元晶体管导通时保持未选择的多个第三存储单元晶体管被施加到第三存储单元晶体管的控制栅极之后，通过向第一存储单元的控制栅极施加高于第二电压的第三电压，将第一存储单元晶体管的阈值电压改变为高于与擦除状态相对应的第一阈值电压的阈值电压晶体管。

55. 发明申请

US20110075489A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110075489A1
公开(公告)日：2011-03-31
申请号：US12718428
申请日：2010-03-05
申请人： Takashi YAMANE , Atsuhiro Sato
发明人： Takashi YAMANE , Atsuhiro Sato
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/3427
摘要： Two or more writing prohibition voltages are applied to bit lines connected to memory cell transistors corresponding to the writing voltage of word lines in a writing operation to write data in the memory cell transistors, while increasing the writing voltage of the word line in a stepwise. Two or more selection gate line voltages, corresponding to the writing prohibition voltages applied to the bit lines, are applied to the gates of selection gate transistors.
摘要翻译：在写入操作中将写入数据写入存储单元晶体管中的两个或多个写入禁止电压施加到与字线的写入电压对应的存储单元晶体管连接的位线，同时逐步增加字线的写入电压。与施加到位线的写入禁止电压对应的两个或多个选择栅极线电压被施加到选择栅极晶体管的栅极。

56. 发明申请

US20100173471A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20100173471A1
公开(公告)日：2010-07-08
申请号：US12720062
申请日：2010-03-09
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧道绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层和第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层和第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅极电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在存储单元晶体管的第一源极和漏极区域，低压晶体管的第二源极和漏极区域以及高压晶体管的第三源极和漏极区域中的衬垫绝缘膜。

57. 发明申请

US20100105177A1 NONVOLATILE SEMICONDUCTOR MEMORY WITH RESISTANCE ELEMENTS AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：具有电阻元件的非线性半导体存储器及其制造方法
公开(公告)号：US20100105177A1
公开(公告)日：2010-04-29
申请号：US12652548
申请日：2010-01-05
申请人： Fumitaka ARAI , Atsuhiro Sato
发明人： Fumitaka ARAI , Atsuhiro Sato
IPC分类号： H01L21/02 , H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539 , H01L29/78
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of the semiconductor substrate, an inter-gate insulating film arranged on the floating gate electrode, a control gate electrode arranged on the inter-gate insulating film, and a source/drain diffusion layer provided in the semiconductor substrate. The resistance element includes an element isolation insulating layer arranged in the semiconductor substrate and including a depression, and a resistor constituted of a second conductive material filling up the depression. An impurity concentration of the second conductive material is lower than that of the first conductive material.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元晶体管和布置在半导体衬底上的电阻元件。存储单元晶体管包括由在半导体衬底的表面上配置在栅极绝缘膜上的第一导电材料构成的浮置栅极电极，布置在浮置栅电极上的栅极间绝缘膜，栅极绝缘膜和设置在半导体衬底中的源极/漏极扩散层。电阻元件包括布置在半导体衬底中并包括凹陷的元件隔离绝缘层和由填充凹陷的第二导电材料构成的电阻器。第二导电材料的杂质浓度低于第一导电材料的杂质浓度。

58. 发明授权

US07705394B2 Nonvolatile semicondutor memory with metallic silicide film electrically connected to a control gate electrode layer 失效
标题翻译：非易失性半导体存储器，其与金属硅化物膜电连接到控制栅电极层
公开(公告)号：US07705394B2
公开(公告)日：2010-04-27
申请号：US11553661
申请日：2006-10-27
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on first, second and third source and drain regions of the memory cell transistor, low voltage transistor, and high voltage transistor, respectively.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高电压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及分别直接设置在存储单元晶体管，低压晶体管和高压晶体管的第一，第二和第三源极和漏极区上的衬垫绝缘膜。

59. 发明授权

US07692252B2 EEPROM array with well contacts 有权
标题翻译：具有良好触点的EEPROM阵列
公开(公告)号：US07692252B2
公开(公告)日：2010-04-06
申请号：US11567805
申请日：2006-12-07
申请人： Atsuhiro Sato , Kikuko Sugimae , Masayuki Ichige
发明人： Atsuhiro Sato , Kikuko Sugimae , Masayuki Ichige
IPC分类号： H01L29/24 , G11C16/04
CPC分类号： H01L27/11519 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area.
摘要翻译：一种半导体集成电路器件，包括：单元阱，形成在单元阱上的存储单元阵列，具有存储单元区域和单元阱接触区域，布置在存储单元区域中的第一布线体以及布置在单元阱中的第二布线体接触面积第二布线体的布局图案与第一布线体的布局图形相同。电池阱接触区域包括具有与电池阱相同的掺杂剂类型的电池阱触点，并且用作在电池阱接触区域中形成的虚拟晶体管的源极/漏极区域。

60. 发明授权

US07663178B2 Nonvolatile semiconductor memory with resistance elements and method of manufacturing the same 失效
标题翻译：具有电阻元件的非易失性半导体存储器及其制造方法
公开(公告)号：US07663178B2
公开(公告)日：2010-02-16
申请号：US11850978
申请日：2007-09-06
申请人： Fumitaka Arai , Atsuhiro Sato
发明人： Fumitaka Arai , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539 , H01L29/78
摘要： A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of the semiconductor substrate, an inter-gate insulating film arranged on the floating gate electrode, a control gate electrode arranged on the inter-gate insulating film, and a source/drain diffusion layer provided in the semiconductor substrate. The resistance element includes an element isolation insulating layer arranged in the semiconductor substrate and including a depression, and a resistor constituted of a second conductive material filling up the depression. An impurity concentration of the second conductive material is lower than that of the first conductive material.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元晶体管和布置在半导体衬底上的电阻元件。存储单元晶体管包括由在半导体衬底的表面上配置在栅极绝缘膜上的第一导电材料构成的浮置栅极电极，布置在浮置栅电极上的栅极间绝缘膜，栅极绝缘膜和设置在半导体衬底中的源极/漏极扩散层。电阻元件包括布置在半导体衬底中并包括凹陷的元件隔离绝缘层和由填充凹陷的第二导电材料构成的电阻器。第二导电材料的杂质浓度低于第一导电材料的杂质浓度。

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