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51. 发明申请

US20060291314A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20060291314A1
公开(公告)日：2006-12-28
申请号：US11473083
申请日：2006-06-23
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603
摘要： A memory capable of performing a refresh operation uncompetitively with an internal access operation also when an external access operation is non-cyclically performed is obtained. This memory comprises an external access detection portion detecting an external access operation, an access control portion performing an internal access operation on the basis of the external access operation and a refresh determination portion determining whether or not to perform a refresh operation on the basis of detection of the external access operation by the external access detection portion and the operating state of the access control portion. The access control portion performs the refresh operation before or after the internal access operation on the basis of the result of determination of the refresh determination portion.
摘要翻译：获得当外部访问操作非周期性地执行时，能够在内部访问操作中无效地执行刷新操作的存储器。该存储器包括检测外部访问操作的外部访问检测部分，基于外部访问操作执行内部访问操作的访问控制部分以及基于检测来确定是否执行刷新操作的刷新确定部分的外部访问检测部分的外部访问操作和访问控制部分的操作状态。访问控制部分基于刷新确定部分的确定结果在内部访问操作之前或之后执行刷新操作。

52. 发明申请

US20060067151A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20060067151A1
公开(公告)日：2006-03-30
申请号：US11228215
申请日：2005-09-19
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C2211/4061 , G11C2211/4067
摘要： A memory capable of performing a refresh operation without increasing current consumption is provided. This memory comprises a plurality of memory cells storing data, a delay circuit outputting a first address signal corresponding to the memory cells received from outside for a normal access operation with a delay of a prescribed period, a refresh control circuit outputting a second address signal corresponding to any of the memory cells subjected to a refresh operation of the data and a switching circuit switching and outputting the first address signal output from the delay circuit and the second address signal output from the refresh control circuit.
摘要翻译：提供了能够在不增加电流消耗的情况下执行刷新操作的存储器。该存储器包括存储数据的多个存储单元，延迟电路，输出与从外部接收的存储单元相对应的第一地址信号，以进行规定周期的延迟的正常访问操作;刷新控制电路，输出相应的第二地址信号对经过数据的刷新操作的任何存储器单元和切换电路进行切换并输出从延迟电路输出的第一地址信号和从刷新控制电路输出的第二地址信号。

53. 发明授权

US08798352B2 X-ray radioscopy device, moving picture processing method, program, and storage medium 有权
标题翻译： X射线透视装置，运动图像处理方法，程序和存储介质
公开(公告)号：US08798352B2
公开(公告)日：2014-08-05
申请号：US12431206
申请日：2009-04-28
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G06K9/00
CPC分类号： G01N23/04 , A61B6/00 , A61B6/542 , A61B6/545 , G01N2223/422 , G06T5/001 , G06T7/11 , G06T2207/10116 , G06T2207/30061
摘要： An X-ray radioscopy device comprises: an image capturing unit that captures a moving image of an object that has been irradiated by X-rays; an analysis processing unit that performs different analysis processes in parallel on each frame that makes up the moving image and extracts, from each frame, a region of interest defined as a portion of the object subject to radioscopy by the X-ray irradiation; and a selection unit that performs an evaluation operation on the multiple regions of interest extracted based on the different analysis processes, and based on the result of the evaluation operation, selects and outputs a single region of interest from the multiple regions of interest extracted by the analysis processing unit.
摘要翻译： X射线摄影装置包括：拍摄被X射线照射的物体的运动图像的图像拍摄单元; 分析处理单元，其在构成运动图像的每个帧上并行地执行不同的分析处理，并从每个帧提取定义为通过X射线照射进行放射线检查的对象的一部分的关注区域; 以及选择单元，其基于不同的分析处理对所提取的多个感兴趣区域执行评估操作，并且基于评估操作的结果，从由所述评估操作提取的所述多个兴趣区域中选择并输出单个感兴趣区域分析处理单元。

54. 发明申请

US20120250974A1 X-RAY IMAGE PROCESSING APPARATUS, X-RAY IMAGE PROCESSING METHOD, AND STORAGE MEDIUM FOR COMPUTER PROGRAM 审中-公开
标题翻译： X-RAY图像处理设备，X射线图像处理方法和计算机程序存储介质
公开(公告)号：US20120250974A1
公开(公告)日：2012-10-04
申请号：US13515999
申请日：2010-12-10
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G06K9/46
CPC分类号： A61B6/504 , A61B6/481 , A61B6/5264 , G06T7/11 , G06T2207/10121 , G06T2207/20224 , G06T2207/30101 , H04N5/325
摘要： An inter-image subtracting unit acquires a subtraction image by performing subtraction processing among a plurality of X-ray images that are obtained when an image of an object is captured at different times. A predetermined-region extracting unit extracts a predetermined region from one of the plurality of X-ray images. A region extracting unit extracts a region based on a contrast-agent injection region from a region of the subtraction image corresponding to the predetermined region.
摘要翻译：图像间减除单元通过在不同时刻拍摄对象的图像时获得的多个X射线图像之中进行减法处理来获取减法图像。预定区域提取单元从多个X射线图像之一中提取预定区域。区域提取单元从对应于预定区域的减法图像的区域中提取基于造影剂注入区域的区域。

55. 发明授权

US07821868B2 Memory and control unit 有权
标题翻译：内存和控制单元
公开(公告)号：US07821868B2
公开(公告)日：2010-10-26
申请号：US12396243
申请日：2009-03-02
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G11C8/00
CPC分类号： G11C11/22 , G11C5/143 , G11C5/144 , G11C5/147 , G11C8/08
摘要： A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an operation rewriting the second address or the amount of the first data and an operation continuously holding the first address and the second address or the amount of the first data.
摘要翻译：存储器包括保持第一数据的第一地址的第一保持电路，保持第一数据的第二地址和第一数据的量中的至少一个的第二保持电路，以及执行重写第一数据的操作的操作控制电路地址，重写第二地址或第一数据量的操作以及持续保持第一地址和第二地址或第一数据量的操作。

56. 发明申请

US20090231904A1 FERROELECTRIC MEMORY WITH SUB BIT-LINES CONNECTED TO EACH OTHER AND TO FIXED POTENTIALS 有权
标题翻译：具有连接到每个其他固定电位的子位线的电介质存储器
公开(公告)号：US20090231904A1
公开(公告)日：2009-09-17
申请号：US12471059
申请日：2009-05-22
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G11C11/22 , G11C5/14 , G11C7/00 , G11C11/24
CPC分类号： G11C11/22
摘要： A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
摘要翻译：获得能够抑制芯片面积的增加同时防止非选择的子阵列受到干扰的存储器。该存储器包括用于将各个子位线彼此连接的第一晶体管，并且通过第一晶体管将非选择的子阵列的子位线彼此连接，并将其连接到布置在存储单元阵列两端的固定电位最少在读操作。

57. 发明授权

US07518944B2 Memory and control unit 有权
标题翻译：内存和控制单元
公开(公告)号：US07518944B2
公开(公告)日：2009-04-14
申请号：US11762566
申请日：2007-06-13
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G11C8/00
CPC分类号： G11C11/22 , G11C5/143 , G11C5/144 , G11C5/147 , G11C8/08
摘要： A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an operation rewriting the second address or the amount of the first data and an operation continuously holding the first address and the second address or the amount of the first data.
摘要翻译：存储器包括保持第一数据的第一地址的第一保持电路，保持第一数据的第二地址和第一数据的量中的至少一个的第二保持电路，以及执行重写第一数据的操作的操作控制电路地址，重写第二地址或第一数据量的操作以及持续保持第一地址和第二地址或第一数据量的操作。

58. 发明授权

US07460425B2 Memory having count detection circuitry for detecting access frequency 有权
标题翻译：具有用于检测存取频率的计数检测电路的存储器
公开(公告)号：US07460425B2
公开(公告)日：2008-12-02
申请号：US11656480
申请日：2007-01-23
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G11C7/00
CPC分类号： G11C11/22 , G11C2029/5002
摘要： A memory capable of suppressing increase in circuit size, reduction in a period for an original access and increase in power consumption while suppressing an imprint can be obtained. The memory includes a first count detection circuit for detecting an access frequency with respect to memory cells, a second count detection circuit for detecting an access frequency of each of memory cell blocks and a third count detection circuit detecting a no-access frequency resulting in an imprint.
摘要翻译：可以获得能够抑制电路尺寸增加，在原始访问期间减少，同时抑制印记而增加功耗的存储器。存储器包括用于检测相对于存储单元的访问频率的第一计数检测电路，用于检测每个存储单元块的访问频率的第二计数检测电路和检测无访问频率的第三计数检测电路，印记。

59. 发明申请

US20070297269A1 MEMORY AND CONTROL UNIT 有权
标题翻译：存储器和控制单元
公开(公告)号：US20070297269A1
公开(公告)日：2007-12-27
申请号：US11762566
申请日：2007-06-13
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G11C5/14 , G11C16/04 , G11C11/22 , G11C11/34 , G11C14/00 , G11C8/00
CPC分类号： G11C11/22 , G11C5/143 , G11C5/144 , G11C5/147 , G11C8/08
摘要： A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an operation rewriting the second address or the amount of the first data and an operation continuously holding the first address and the second address or the amount of the first data.
摘要翻译：存储器包括保持第一数据的第一地址的第一保持电路，保持第一数据的第二地址和第一数据的量中的至少一个的第二保持电路，以及执行重写第一数据的操作的操作控制电路地址，重写第二地址或第一数据量的操作以及持续保持第一地址和第二地址或第一数据量的操作。

60. 发明申请

US20070253274A1 MEMORY 有权
标题翻译：记忆
公开(公告)号：US20070253274A1
公开(公告)日：2007-11-01
申请号：US11739754
申请日：2007-04-25
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G11C8/00
CPC分类号： G11C11/22
摘要： A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
摘要翻译：获得能够抑制芯片面积的增加同时防止非选择的子阵列受到干扰的存储器。该存储器包括用于将各个子位线彼此连接的第一晶体管，并且通过第一晶体管将非选择的子阵列的子位线彼此连接，并将其连接到布置在存储单元阵列两端的固定电位最少在读操作。

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