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51. 发明授权

US07269088B2 Identical chips with different operations in a system 有权
标题翻译：在系统中具有不同操作的相同芯片
公开(公告)号：US07269088B2
公开(公告)日：2007-09-11
申请号：US11131572
申请日：2005-05-17
申请人： Randy B. Osborne
发明人： Randy B. Osborne
IPC分类号： G11C8/00
CPC分类号： G11C5/00 , G11C7/1051 , G11C7/1075 , G11C7/1078
摘要： In some embodiments, a chip includes a memory core, control circuitry, and first ports, second ports, and third ports. The first ports are to only receive signals, the second ports are to only provide signals, and the control circuitry is to control whether the third ports are to only receive signals or only provide signals. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括存储器核心，控制电路以及第一端口，第二端口和第三端口。第一个端口只能接收信号，第二个端口只能提供信号，控制电路是控制第三个端口是仅接收信号还是只提供信号。描述和要求保护其他实施例。

52. 发明授权

US06978351B2 Method and system to improve prefetching operations 失效
标题翻译：改进预取操作的方法和系统
公开(公告)号：US06978351B2
公开(公告)日：2005-12-20
申请号：US10335424
申请日：2002-12-30
申请人： Randy B. Osborne , Kenneth C. Creta , Joseph A. Bennett , Jasmin Ajanovic
发明人： Randy B. Osborne , Kenneth C. Creta , Joseph A. Bennett , Jasmin Ajanovic
IPC分类号： G06F12/00 , G06F12/08 , G06F13/42
CPC分类号： G06F13/4243
摘要： To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.
摘要翻译：为了在沿着从输入 - 输出总线到系统存储器的路径预取部分数据集时减少预取过冲，使用预取字段来传送预取实体上游可能预取的数据量。以这种方式利用预取字段减少了在所请求的数据的结尾之后提取不需要的数据，导致整体上提高的系统性能。

53. 发明授权

US06877052B1 System and method for improved half-duplex bus performance 失效
标题翻译：改善半双工总线性能的系统和方法
公开(公告)号：US06877052B1
公开(公告)日：2005-04-05
申请号：US09675991
申请日：2000-09-29
申请人： Randy B. Osborne
发明人： Randy B. Osborne
IPC分类号： G06F13/00 , G06F13/364
CPC分类号： G06F13/364
摘要： A method for dynamic preemption of read returns over a half-duplex bus during heavy loading conditions involves asserting a preempt signal by a first agent to indicate that the first agent has a read request pending for transmission over the half-duplex bus. A second agent then samples the preempt signal sent by the first agent. The second agent relinquishes ownership of the half-duplex bus responsive to the preempt signal to allow the read request to be sent across the half-duplex bus.
摘要翻译：在重负载条件期间通过半双工总线动态抢占读取返回的方法包括由第一代理确定先占信号，以指示第一代理具有等待通过半双工总线传输的读请求。然后，第二代理对第一代理发送的抢占信号进行采样。响应于抢占信号，第二代理人放弃半双工总线的所有权，以允许在半双工总线上发送读请求。

54. 发明授权

US06792496B2 Prefetching data for peripheral component interconnect devices 有权
标题翻译：预取外围组件互连设备的数据
公开(公告)号：US06792496B2
公开(公告)日：2004-09-14
申请号：US09922235
申请日：2001-08-02
申请人： Nagi Aboulenein , Randy B. Osborne
发明人： Nagi Aboulenein , Randy B. Osborne
IPC分类号： G06F1200
CPC分类号： G06F13/4031 , G06F12/0862 , G06F2212/1024
摘要： Prefetching data includes issuing a first request to prefetch data from a memory, receiving a response to the first request from the memory, obtaining a measure of latency between the first request and the response, and controlling issuance of a subsequent request to prefetch other data from the memory based on the measure.
摘要翻译：预取数据包括发出第一请求以从存储器预取数据，从存储器接收对第一请求的响应，获得第一请求和响应之间的等待时间的度量，以及控制发送后续请求以从其中取出其他数据基于测量的记忆。

55. 发明授权

US06718512B2 Dynamic parity inversion for I/O interconnects 有权
标题翻译： I / O互连的动态奇偶校验反转
公开(公告)号：US06718512B2
公开(公告)日：2004-04-06
申请号：US10360339
申请日：2003-02-06
申请人： Randy B. Osborne , Jasmin Ajanovic
发明人： Randy B. Osborne , Jasmin Ajanovic
IPC分类号： G06F1100
CPC分类号： H04L1/0061 , H04L1/004 , H04L7/0083 , H04L7/048
摘要： A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.
摘要翻译：或者（b）在发送代理向接收代理发送的数据的传送期间检测同步错误的方法：（a）当发送代理在一个或多个时钟信号中对数据进行编码时，（a）用数据奇偶校验功能编码的数据奇偶校验，）标题奇偶校验，当发送代理编码一个或多个时钟信号中的标题信息时，用标题奇偶校验功能编码。当接收方：（a）被配置为接收数据奇偶校验并且实际接收到标题奇偶校验时，或者（b）被配置为接收标题奇偶校验并实际接收数据奇偶校验，则检测到同步错误状况。

56. 发明授权

US06587988B1 Dynamic parity inversion for I/O interconnects 失效
公开(公告)号：US06587988B1
公开(公告)日：2003-07-01
申请号：US09469397
申请日：1999-12-22
申请人： Randy B. Osborne , Jasmin Ajanovic
发明人： Randy B. Osborne , Jasmin Ajanovic
IPC分类号： G06F1100
CPC分类号： H04L1/0061 , H04L1/004 , H04L7/0083 , H04L7/048
摘要： A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

57. 发明授权

US06483507B2 Super-sampling and gradient estimation in a ray-casting volume rendering system 有权
标题翻译：射线投射体绘制系统中的超采样和梯度估计
公开(公告)号：US06483507B2
公开(公告)日：2002-11-19
申请号：US09862901
申请日：2001-05-22
申请人： Randy B. Osborne , Ingmar Bitter , Hanspeter Pfister , James Knittel , Hugh C. Lauer
发明人： Randy B. Osborne , Ingmar Bitter , Hanspeter Pfister , James Knittel , Hugh C. Lauer
IPC分类号： G06T1500
CPC分类号： G06T15/08 , G06T15/005 , G06T15/10
摘要： A volume rendering processor renders a two-dimensional image from a volume data set of voxels constituting a three-dimensional representation of an object. Voxel memory interface logic retrieves the voxels from a voxel memory in a scanned order with respect to X, Y and Z coordinate axes, the Z axis being the axis most nearly parallel to a predefined viewing direction. The set of voxels having equal Z coordinate values are referred to as a “slice” of voxels. Interpolation logic calculates a sequence of samples from the retrieved voxels such that (i) each sample lies along a corresponding imaginary ray extending through the object parallel to the viewing direction, (ii) each sample results from interpolating the eight voxels surrounding the sample in the XYZ coordinate system. “Supersampling” in the Z dimension is performed such that the number of samples calculated for each ray is greater than the number of slices of voxels in the volume data set. Gradient calculation logic calculates for each sample respective gradients in the X, Y and Z directions for use by classification and illumination logic. The X and Y gradients are calculated from the samples emitted by the interpolation logic, and Z gradients are calculated by (i) calculating Z gradients at the voxel positions from voxel values retrieved from memory, and (ii) interpolating the voxel Z gradients to arrive at the Z gradients at the sample positions.
摘要翻译：体绘制处理器从构成对象的三维表示的体素数据集合呈现二维图像。体素存储器接口逻辑以相对于X，Y和Z坐标轴的扫描顺序从体素存储器检索体素，Z轴是最接近平行于预定观察方向的轴。具有相等Z坐标值的一组体素被称为体素的“切片”。插值逻辑从所检索的体素计算样本序列，使得（i）每个样本沿着平行于观察方向延伸穿过物体的相应假想射线位于（ii）每个样本由内插样本周围的八个体素 XYZ坐标系。执行Z维度中的“超采样”，使得针对每个射线计算的样本数量大于体数据集中体素的数量。梯度计算逻辑计算X，Y和Z方向上每个样本各个梯度的分类和照明逻辑使用的梯度。由内插逻辑发射的样本计算X和Y梯度，并且（i）通过（i）从存储器检索的体素值计算体素位置处的Z梯度来计算Z梯度，以及（ii）内插体素Z梯度以到达在Z样品位置的梯度。

58. 发明授权

US06243098B1 Volume rendering pipelines 有权
标题翻译：体积渲染管线
公开(公告)号：US06243098B1
公开(公告)日：2001-06-05
申请号：US09318344
申请日：1999-05-25
申请人： Hugh C. Lauer , Randy B. Osborne , Hanspeter Pfister
发明人： Hugh C. Lauer , Randy B. Osborne , Hanspeter Pfister
IPC分类号： G06T1500
CPC分类号： G06T15/08 , G06T1/60 , G06T15/005 , G06T15/40
摘要： An apparatus renders a volume data set including a plurality of voxels stored in a voxel memory. The apparatus includes a plurality of pipelines operating in parallel. Each pipeline includes a buffer storing at least one block of at least two voxels of the volume data set. An interpolation stage reads the at least one block of at least two voxels from the buffer. A gradient estimation stage receives an output from the interpolation stage. A compositing stage receives an output from the gradient estimation stage. The apparatus also includes a plurality of interface devices, wherein each interface device couples a particular stage only to an adjacent identical stage in a neighboring pipeline so that identical stages of the pipelines are connected in a ring.
摘要翻译：装置呈现包括存储在体素存储器中的多个体素的体数据集。该装置包括并行操作的多条管线。每个流水线包括存储体数据集的至少两个体素的至少一个块的缓冲器。内插级从缓冲器读取至少两个体素的至少一个块。梯度估计级接收来自插值级的输出。合成阶段接收梯度估计阶段的输出。该设备还包括多个接口设备，其中每个接口设备仅将特定级联在相邻管线中的相邻相同级，使得管道的相同级连接在环中。

59. 发明授权

US5909546A Network interface having support for allowing remote operations with reply that bypass host computer interaction 失效
公开(公告)号：US5909546A
公开(公告)日：1999-06-01
申请号：US614834
申请日：1996-03-08
申请人： Randy B. Osborne
发明人： Randy B. Osborne
IPC分类号： G06F13/00 , G06F13/12 , H04L12/56 , H04Q3/00 , G06F15/16
CPC分类号： G06F13/128 , H04L49/90
摘要： A network interface for a connection-based communication network has support for remote operations with reply, such as a remote read operation, that bypass host computer interaction. Such a network interface has support for general message processing operations which bypass host processor involvement. Message processing is low level processing of message between the host computer and the network. Such processing is performed on transmission in response to control information provided by the host and is performed on reception in response to control information included in incoming messages. Message processing includes low latency remote read and remote write operations, message filtering, and message demultiplexing. Such a network interface handles incoming messages containing destination control information indicating an operation to be performed, and possibly one or more operands. The network interface processes destination control information from a received message using a message coprocessor or equivalent operational logic. For such a network interface to support message processing, it includes mechanisms for extracting destination control information from a message and for inserting destination control information into a message. The network interface maintains information for each connection that indicates where the destination control information is located in any message received or transmitted over the connection. By providing for a queue of transmit requests between the receive and transmit sides on the network interface, support is provided for remote read operations or other operations invoking a reply which bypass the host processor. The queue can be appended by the receive side in response to a message processing operation performed on a received message. The queue is read by the transmit side to generate an outgoing message as if the queue provided transmit requests like the host computer.

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