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    • 51. 发明专利
    • Manufacture of semiconductor device
    • 半导体器件的制造
    • JPS61120432A
    • 1986-06-07
    • JP24061084
    • 1984-11-16
    • Hitachi Ltd
    • SATO TOSHIHIKOKASAHARA OSAMU
    • H01L21/52H01L21/58H01L21/60H01L23/52
    • H01L24/83H01L24/29H01L24/81H01L24/94H01L2224/16145H01L2224/291H01L2224/29144H01L2224/83101H01L2224/8319H01L2224/83805H01L2224/8385H01L2224/94H01L2924/0105H01L2924/01079H01L2924/0132H01L2924/01322H01L2924/07802H01L2224/81H01L2924/01014H01L2924/00
    • PURPOSE:To reduce the thermal resistance in a bond section, by mounting chips on a semiconductor substrate through flip-chip-type projection electrodes, applying a metallic layer on the rear face of the substrate at a temperature lower than the melting point of the projection electrodes and bonding the metallic layer to a package substrate with a low-melting brazing material. CONSTITUTION:Semiconductor chips 2 are electrically connected to the surface of a mother chip 1 provided with wirings, by means of flip-chip-type projection electrodes 3. While the chip side of the mother chip 1 is cooled, Au and Si are simultaneously spattered thereon to provide a metallic layer 4. After dicing the mother chip, the diced mother chip 1 is overlayed on a package substrate 8 provided with an Au metallized layer 7 by means of a low-melting brazing material of Au.Sn foil 6 and heat treated so that the mother chip 1 is firmly bonded to the package substrate 8. According to this method, the thermal resistance in the bonded section is reduced and therefore the heat-dissipating efficiency of the chips 2 can be improved.
    • 目的:为了降低接合部的热阻,通过倒装芯片型突起电极将芯片安装在半导体基板上,在低于突起的熔点的温度下在基板的背面上涂布金属层 电极,并用低熔点钎焊材料将金属层粘合到封装衬底上。 构成:半导体芯片2通过倒装芯片型突起电极3与配有布线的母芯片1的表面电连接。母芯片1的芯片侧被冷却时,Au和Si同时溅出 在其上切割母芯片后,通过Au.Sn箔6的低熔点钎焊材料和加热的热量将切割的母芯片1覆盖在设有Au金属化层7的封装衬底8上 进行处理,使得母芯片1牢固地结合到封装基板8.根据该方法,结合部分的热阻降低,因此可以提高芯片2的散热效率。
    • 52. 发明专利
    • MULTILAYER INTERCONNECTION MEMBER
    • JPS60245252A
    • 1985-12-05
    • JP10045984
    • 1984-05-21
    • HITACHI LTD
    • KASAHARA OSAMUSASABE SHIYUNJI
    • H01L23/522H01L21/768
    • PURPOSE:To improve the reliability of the titled member by a method wherein the second conductive layer serving as an etching stopper is provided on the first conductive layer, and the insulation between the second layer wiring and the third layer wiring is improved by homogenizing the insulation film covering the second layer wiring. CONSTITUTION:A field insulation layer 2 and an insulation layer 3 are formed in the main surface part of a required region of a substrate 1. The first layer wiring 4 is formed in a required region of the upper surface part of the insulation layer 3; thereafter, an insulation layer 5 is formed. Conductive layers 7, 7A are formed to fill a connection hole 6, and conductive layers 8, 8A made of Cu or Cu alloy are formed on the conductive layers 7, 7A to form an etching inhibition member 8. After the photo resist layer 13 on this member 8 is removed, the second layer wiring 9 is formed. Thereafter, the second layer wiring 10 and the third layer wiring 11 are formed. Since an eye open 9A does not allow the formation of crevasses in the second layer wiring 9 and the third layer wiring 11, the film quality of the second insulation layer 10 is made uniform, and the electric insulation of those layers can be improved.
    • 55. 发明专利
    • SPUTTERING DEVICE
    • JPS586973A
    • 1983-01-14
    • JP10446381
    • 1981-07-06
    • HITACHI LTD
    • OOGISHI HIDEJIKASAHARA OSAMU
    • C23C14/34H01J37/34H01L21/285H01L21/31
    • PURPOSE:To provide a titled device which can prevent the inclusion of the material of a shielding ring into a sputtering film by differing the potential upon a target material and the shielding ring and interposing a guard ring for preventing electric discharge between the shielding ring and a magnet. CONSTITUTION:In this sputtering device, a shielding ring 32 is fixed to a sputtering shield 30 grounded to the earth potential and therefore the potential of the ring 32 differs from the potential of a target material 4. Therefore, if high frequency electric power is applied from a high frequency electric power source 10, only the Si material of the material 14 is sputtered without sputtering the side surface on the target plate 14 side of the ring 32, whereby an Si sputtering film of high purity is stuck and deposited on a substrate. Since a guard ring 34 is interposed between the ring 32 and a magnet 20, the generation of the abnormal electric discharge between the ring 32 and the magnet 20 is inhibited.
    • 56. 发明专利
    • MANUFACTURING OF SEMICONDUCTOR DEVICE
    • JPS56124245A
    • 1981-09-29
    • JP2430281
    • 1981-02-23
    • HITACHI LTD
    • KASAHARA OSAMUMASUOKA KIYOTAKE
    • H01L21/60H01L21/28H01L23/532H01L29/43
    • PURPOSE:To prevent an Si substrate and an aluminum wiring from mutual dispersion by providing a silicified platinum layer between them, and also to prevent an SiO2 membrane from exfoliation by providing an aluminum pad on its surface. CONSTITUTION:A base emitter layer is formed on an Si substrate 1. As for the emitter layer, SiO2 4 is provided with an opening, Pt is attached by soldering and heated to selectively form Pt-Si layer 6 so as to prevent mutual dispersion between Si and Al. And then, a wiring layer for two layers of Mo 7 and Al 9 is provided, covered with SiO2 10 and an opening 11 is selectively provided. An Al wiring 12a and a joining pad 12b for the second layer are provided at the opening, and an Al wiring is joined to the pad 12b by supersonic wave. In this mechanism, since the Al pad 12b and the SiO2 membrane 4 are joined together directly, the joining strength become large, and in the case of a thermal oxide membrane, in particular, since the membrane is much harder than a CVD membrane, the joint is ensured. Further, as compared with an Al-Mo dual structure pad, possibility of exfoliation of the pad becomes as small as less than 1%.