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51. 发明专利

JPH0540746A INFORMATION PROCESSOR 失效
公开(公告)号：JPH0540746A
公开(公告)日：1993-02-19
申请号：JP19772191
申请日：1991-08-07
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIBATA KATSUNARI , YAMADA MINORU , MASUDA NOBORU , YAGYU MASAYOSHI , YASUNAGA MORITOSHI , ASAI MITSUO , SAKAGUCHI TAKAHIRO , HASHIMOTO MASA
IPC分类号： G06F15/18 , G06G7/60 , G06N3/08 , G06N99/00
摘要： PURPOSE:To automatically learn an evaluation function and to automatically and efficiently learn an operating signal from the evaluation function without giving a teacher signal from outside. CONSTITUTION:The first arithmetic processing part 301 which calculates an operating signal 405 from an input data 400 which changes according to time lapse by using a variable arithmetic coefficient and the first teacher signal generating part 304 which generates a teacher signal from the value of an evaluation function which receives data from the input data 400 are provided. At the first teacher signal generating part 304, the value of the evaluation function is calculated by the second arithmetic processing part 343 having a variable arithmetic coefficient, and the second teacher signal generating part 345 generates a teacher signal for the second arithmetic processing part 343 from the output fluctuation according to time lapse, and the second arithmetic processing part 343 outputs a evaluation function. Learning is made in order to perform these procedures.

52. 发明专利

JPH0464230A LARGE-AREA INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0464230A
公开(公告)日：1992-02-28
申请号：JP17521290
申请日：1990-07-04
申请人： HITACHI LTD
发明人： MASUDA NOBORU , YASUNAGA MORITOSHI , YAGYU MASAYOSHI , ASAI MITSUO , SHIBATA KATSUNARI , YAMADA MINORU
IPC分类号： H01L21/3205 , H01L21/027 , H01L23/52
摘要： PURPOSE:To expose a wiring efficiently by forming a wiring layer for wiring and connecting the chips of an integrated circuit and a wiring layer for wiring in the chips in common. CONSTITUTION:When a chip 1 is irradiated with light, a section 50 in 11 is brought to the shade of a photo-mask, and light is applied only to a section 60. Consequently, light is applied to a section 61, and a section 51 is brought to the shade. No light is applied to the outside of an irradiation range 11, the right side from a longitudinal solid line, naturally at that time. When a chip 2 is irradiated with light, the section 50 in 12 is also brought to the shade of the photo-mask and light is also applied only to the section 60, but light is also applied to the section 61 and the section 51 is also brought to the shade at that time. When the whole is developed, a photo-resist remains to the section 50 including 51, and finally the metallic film of wiring is left in the section 50 including 51.

53. 发明专利

JPH02255908A CLOCK SIGNAL SUPPLYING DEVICE AND ELECTRONIC COMPUTER 失效
公开(公告)号：JPH02255908A
公开(公告)日：1990-10-16
申请号：JP31523589
申请日：1989-12-06
申请人： HITACHI LTD
发明人： ISHIBASHI KENICHI , HAYASHI TAKEHISA , DOI TOSHIO , ASAI MITSUO , MASUDA NOBORU , YAMAGIWA AKIRA , OKABE TOSHIHIRO
IPC分类号： G06F1/10 , G11C11/407
摘要： PURPOSE:To decrease the number of clock signals to be supplied and at the same time to produce a clock signal having the reduced skew by supplying a standard 1st clock signal in order to produce a multi-phase clock signal in each processor. CONSTITUTION:A clock signal production part 10 produces a 1st clock signal of a single phase as a basic clock signal and supplies it to each processor 50 via a signal line 30. The processor 50 contains a phase control part 41 and a clock signal generating part 42. The part 41 compares the phase of a basic clock signal with that of the basic clock signal and controls the phase of the basic clock signal so that the coincidence is secured between both signals. The part 42 measures and controls the delay time of a variable delay circuit 51 of the part 41 and produces a multi-phase 2nd clock signal. This clock signal is supplied to each FF 46 via a distribution circuit 43. In such a constitution, the number of clock signals supplied to each processor 50 can be decreased. Then a multi-phase clock signal having the reduced skew can be produced in each processor 50.

54. 发明专利

JPH02181284A NEURAL NETWORK 失效
公开(公告)号：JPH02181284A
公开(公告)日：1990-07-16
申请号：JP30089
申请日：1989-02-10
申请人： HITACHI LTD
发明人： ASAI MITSUO , HAYASHI TAKEHISA , DOI TOSHIO , ISHIBASHI KENICHI , YAMADA MINORU
IPC分类号： B65H3/24 , B65H3/30 , G06F15/18 , G06J1/00 , G06N3/04 , G06N99/00
摘要： PURPOSE:To process the data of a large scale with a small area by using a means which converts the output value of an output terminal into a pulse signal that shows its value in the pulse width or the pulse density. CONSTITUTION:All output terminals 71 of N pieces of neuron circuits 4 are connected to a time division broadcast network 35. The output values received from the terminals 71 are referred to as x0, x1 - xn-1, then, the network 35 selects one of these output values and outputs successively the values x0 - xn-1 to a digital/PWM converter 13. The converter 13 converts the received value into a pulse signal having the pulse width or the pulse density proportional to the output value of the circuit 4 and sends this pulse signal to the input terminal of the circuit 4. Thus all data necessary for the circuits 4 are secured by repeating these actions by N times. As a result, just a single synopsis circuit 2 is required for each circuit 4 owing to a fact that the product sum arithmetic is carried out in time division. Therefore the hardware quantity is extremely reduced.

55. 发明专利

JPH11146325A VIDEO RETRIEVAL METHOD, DEVICE THEREFOR, VIDEO INFORMATION GENERATING METHOD AND STORAGE MEDIUM STORING ITS PROCESSING PROGRAM 失效
公开(公告)号：JPH11146325A
公开(公告)日：1999-05-28
申请号：JP30745997
申请日：1997-11-10
申请人： HITACHI LTD
发明人： MORITA KOICHI , ASAI MITSUO , ISHIDA TOMOYUKI , ONODERA TAKESHI , TAKIYASU YOSHIHIRO
IPC分类号： G06F3/14 , G06F3/048 , G06F17/30 , G11B27/00 , G11B27/034 , G11B27/10 , G11B27/28 , G11B27/34 , H04N5/76 , H04N5/78
摘要： PROBLEM TO BE SOLVED: To provide the video retrieval method and the system having a function of expressing a video file so that contents of the video file stored in a storage device are clearly recognized. SOLUTION: The video retrieval method and system are provided with a function of expressing contents of video files stored in a storage device 103 by a group image consisting of still images at least with two scenes, and also with a function of revising a size of the group image at any time, a file operation function delete, movement, and name change or the like for the corresponding video file by the operation on the group image, a function of generating a digest where scene still images are displayed at a predetermined interval with respect to each video file in the case of confirming in detail contents of the stored video files, a function of generating another digest with respect to each interval of the digested video files, and a function of program-searching and reproducing the scene still image selected on the digested video files.

56. 发明专利

JPH10164176A COMMUNICATION METHOD 失效
公开(公告)号：JPH10164176A
公开(公告)日：1998-06-19
申请号：JP27164297
申请日：1997-10-03
申请人： HITACHI LTD
发明人： ONO RYUICHI , ASAI MITSUO , YAMASHITA YOJI , TAKIYASU YOSHIHIRO
IPC分类号： H04L29/08
摘要： PROBLEM TO BE SOLVED: To effectively transmit and receive the data even in a fast communication mode set for transfer of animations, etc., by securing the logical connection between the transmitting and receiving terminals, securing the correspondence between the receiving and transmitting requests by means of the identifiers added to both requests, and transferring the data to the receiving terminal from the transmitting terminal. SOLUTION: The computers 400 and 460 are connected to each other via a network 430, and the lower order protocol modules 406 and 466 control the data transmission function between both computers. Then an application or higher order protocol modules 402 and 462 designate an identifier of a receiving computer and an identifier that identifies the receiving opposite party of the receiving computer or a connection identifier to the middle order protocol modules 404 and 464 to perform the logical connection, to designate the designation of data, etc. Furthermore, a transmitting/receiving buffer, its length, etc., are designated for designation of the storing places of data to be transmitted and received.

57. 发明专利

JPH1091575A DIGITAL VIDEO STORAGE SERVER AND ITS DATA TRANSFER METHOD 失效
公开(公告)号：JPH1091575A
公开(公告)日：1998-04-10
申请号：JP24279196
申请日：1996-09-13
申请人： HITACHI LTD
发明人： ASAI MITSUO , SHIBATA KOICHI , TAKIYASU YOSHIHIRO , YAMASHITA YOJI
IPC分类号： G06F13/36
摘要： PROBLEM TO BE SOLVED: To decrease the conflict of an I/O bus between the transfer of data to a memory from a disk device and the transfer of data to a network from the memory and also to decrease the bus wait cycles that are caused by the latency occurring in a memory read mode. SOLUTION: Two data transfer operations properly use the I/O buses 107 and 103 respectively. In regard to a transfer path led to a memory 134 from a storage adaptor 150, the data are quickly transferred in parallel to each other by the write commands which are continuously issued and a pipeline operation despite a large number of pipeline stages. A transfer path having a small number of buses to pass through is selected between the memory 134 and a communication adapter 120, so that the bus wait cycles are decreased. When the data are transferred from a network 123 to a disk device 153, a memory 144 is used as a buffer and a path having a small number of buses to pass through in a memory read mode is selected.

58. 发明专利

JPH09265416A HIERARCHICAL INFORMATION MANAGEMENT METHOD AND EXECUTION DEVICE FOR THE METHOD 失效
公开(公告)号：JPH09265416A
公开(公告)日：1997-10-07
申请号：JP7343796
申请日：1996-03-28
申请人： HITACHI LTD
发明人： SAITO ATSUSHI , YAMASHITA YOJI , TAKIYASU YOSHIHIRO , MATSUZAWA SHIGERU , ASAI MITSUO
IPC分类号： G06F12/00
摘要： PROBLEM TO BE SOLVED: To uniformly execute storage area allocation to a higher layer storage device to plural users by allocating a selected storage area inside the higher layer storage device to the user to newly access the higher layer storage device. SOLUTION: By an access state monitor 120, for the respective storage areas of the divided plural storage areas of the higher layer storage device, an area state management table 100 storing access information including users for each time width of a specified length and the number of times of access is prepared. By an area state monitor 110, the access information for each user in the area state management table 100 is referred to, whether or not a free area is present inside the higher layer storage device is checked, and in the case that the plural free areas are present, the one specified storage area among them is selected as the storage area to be allocated to the newly accessing user. In the case that the tree area is not present, when the plural storage areas accessed by a single user are present, one storage area among them is selected.

59. 发明专利

JPH0970028A METHOD FOR DELIVERING PLURAL VIDEO IMAGES 失效
公开(公告)号：JPH0970028A
公开(公告)日：1997-03-11
申请号：JP22281995
申请日：1995-08-31
申请人： HITACHI LTD
发明人： MISHINA YUSUKE , TAKIYASU YOSHIHIRO , ASAI MITSUO , KIN INKI , SATOU MIKIKO , IGAWA MASARU , SHIBATA KOICHI
IPC分类号： G06F13/00 , H04L12/54 , H04L12/58 , H04N7/10 , H04N7/173 , H04N21/8547
摘要： PROBLEM TO BE SOLVED: To obtain the method for delivering plural video images in which delivered video images are synchronized with each other so that a client displays continuously plural video images from plural servers without interruption. SOLUTION: In the system consisting of a delivery server A for a preceding video image and a delivery server B for a succeeding video image, the server B uses a synchronization data delivery control program 233 to deliver synchronization data at a prescribed interval. A client 260 detects data of a closer reception time as to received preceding video data and synchronization data by using a synchronization frame information detection program 280 and obtains a start timing of a succeeding video image based on the data in pairs and final data of the preceding video image. As a result, clock matching between the server and the client is not required. Since it is not required to provide a synchronization buffer area for the succeeding video image to a reception buffer of the client, the storage capacity is saved.

60. 发明专利

JPH0855036A TASK SCHEDULING METHOD 失效
公开(公告)号：JPH0855036A
公开(公告)日：1996-02-27
申请号：JP21063294
申请日：1994-08-11
申请人： HITACHI LTD
发明人： SHIBATA KOICHI , ASAI MITSUO , SATOU MIKIKO , TAKIYASU YOSHIHIRO , SAITO ATSUSHI
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To make the average performance of a system and its real time property compatible by determining a task execution order from information relating to inter-task continuity and dead lines included in execution starting requests from respective tasks by a scheduler. CONSTITUTION:Activation permission requests 103a to 103c from respective processing tasks 101a to 101c are received in an activation permission request queue 104. When the scheduler 102 is activated, an insertion and rearrangement step 105 is operated and the activation permission requests 103a to 103c from the respective processing tasks are taken out from the activation permission request queue 104 and inserted in a task chart 106. At the time, the execution of the tasks is basically permitted in the order of the starting time limits. Then, as long as the completion dead lines of the respective tasks are kept, the task with high continuity is successively selected. In the meantime, when the execution of the task with the high degree of urgency is requested, the task close to the completion dead line is selected and preferentially executed. Thus, the overhead of task transition is reduced and the dead line is kept.

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