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51. 发明授权

US5233206A Double digitlines for multiple programming of prom applications and other anti-fuse circuit element applications 失效
标题翻译：双程数字线用于舞台应用和其他抗熔丝电路元件应用的多重编程
公开(公告)号：US5233206A
公开(公告)日：1993-08-03
申请号：US791808
申请日：1991-11-13
申请人： Roger R. Lee , Tyler A. Lowrey , D. Mark Durcan
发明人： Roger R. Lee , Tyler A. Lowrey , D. Mark Durcan
IPC分类号： G11C17/16 , H01L23/525
CPC分类号： H01L27/1021 , G11C17/16 , H01L23/5252 , H01L2924/0002
摘要： The present invention provides a programmable structure for programmable integrated circuits, such as programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digitlines as well as on the wordlines thereby providing two, one time programmable nodes at each digit/word/digit' intersection. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines, also having one-sided ozone spacers, and further overlying parallel rows' of digitlines' in a programmable read only memory. With a lower level of digitlines passing under a middle level of wordlines and an upper level of digitlines' passing over the middle level of wordlines, a row/column/digit' matrix is formed thereby providing a programmable row/column/row' matrix in a memory array. Each crossing point of the digit/word lines and the word/digit' lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word/digit' line conductors.
摘要翻译：本发明提供了一种用于可编程集成电路的可编程结构，诸如可编程只读存储器（PROM），其利用在数字线上以及字线上构造的单面臭氧间隔物，从而在每个数字处提供两个一次可编程节点 /字/数字'十字路口。氧化物/氮化物/氧化物层（ONO）用作下列平行的数字行行之间的界面，其具有单面臭氧间隔物，并且覆盖平行的字线列，也具有单面臭氧间隔物，并且进一步覆盖平行可编程只读存储器中的行“行”。在较低级别的数字线通过字线的中间级别和数字线的较高级别通过字线的中间级别时，形成行/列/数字矩阵，从而提供可编程的行/列/行矩阵一个存储器阵列。数字/字线的每个交叉点和矩阵中的字/数字线将通过在相关联的数字/字/字之间施加适当的电压电位来破坏薄ONO电介质接口而被永久编程为一个或一个零，数字“线导体。

52. 发明授权

US5013680A Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography 失效
标题翻译：用于制造具有超越可用光刻的分辨率极限的特征宽度的DRAM阵列的工艺
公开(公告)号：US5013680A
公开(公告)日：1991-05-07
申请号：US555980
申请日：1990-07-18
申请人： Tyler A. Lowrey , Randal W. Chance , D. Mark Durcan , Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Fernando Gonzalez , Gordon A. Haller
发明人： Tyler A. Lowrey , Randal W. Chance , D. Mark Durcan , Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Fernando Gonzalez , Gordon A. Haller
IPC分类号： H01L21/033 , H01L21/308 , H01L21/334 , H01L21/336 , H01L21/762 , H01L21/768 , H01L21/8242
CPC分类号： H01L27/10864 , H01L21/033 , H01L21/3086 , H01L21/76232 , H01L21/768 , H01L29/66181 , H01L29/66666 , Y10S438/947
摘要： A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidistanty-spaced isolation trenches in a silicon substrate; filling the isolation trenches with insulative material; creation of a hard-material mask consisting of strips that are 1-1/2F in width, separated by spaces that are 1/2F in width, that is used to etch a matrix of storage trenches; angled implantation of a N-type impurity in the storage trench walls; another anisotropic etch to deepen the storage trenches; deposition of a capacitor dielectric layer; deposition of a protective polysilicon layer on top of the dielectric layer; removal of the dielectric layer and the protective polysilicon layer at the bottom of each storage trench with a further anisotropic etch; filling the storage trenches with in-situ-doped polysilicon; planarization down to the substrate level; creation of an access gate on opposite sides of each storage trench, in addition to wordlines which interconnect gates within array columns by anisotropically etching a conformal conductive layer that has been deposited on top of oxide-silicon mesas that run perpendicular to the isolation trenches and are centered between the rows of storage trenches, the oxide-silicon mesas having been created with an etch using a photoresist mask consisting of a series of parallel strips that have been laid down with minimum feature and space width, then plasma etched to 3/4F; creation of source and drains with an N-type implant; and anisotropically etching the metal layer to create bitlines along the sidewalls of the oxide mesas.
摘要翻译：一种用于创建DRAM阵列的方法，其具有仅使用五个光掩模步骤超越所使用的光刻工艺的分辨率极限的特征宽度。该方法包括以下步骤：产生半间距硬材料掩模，其用于蚀刻硅衬底中的一系列等间隔隔开的隔离沟槽; 用绝缘材料填充隔离沟; 由宽度为1-1 / 2F的条形成的宽度为1 / 2F的间隔的用于蚀刻存储沟槽的矩阵的硬质材料掩模的形成; 在存储沟槽壁中倾斜注入N型杂质; 另一种各向异性蚀刻来加深存储沟槽; 沉积电容器电介质层; 保护性多晶硅层在电介质层的顶部上沉积; 通过进一步的各向异性蚀刻在每个存储沟槽的底部去除电介质层和保护性多晶硅层; 用原位掺杂多晶硅填充存储沟槽; 平坦化到底层水平; 在每个存储沟槽的相对侧上形成存取栅极，除了通过各向异性蚀刻已经沉积在垂直于隔离沟槽的氧化物 - 硅台面顶部上的共形导电层来互连阵列列内的栅极的字线之外，并且是在存储沟槽的行之间居中，使用由具有最小特征和空间宽度放置的一系列平行条组成的光刻胶掩模，然后将等离子体蚀刻到3 / 4F，利用蚀刻产生氧化物 - 硅台面; 用N型植入物创建源和排水沟; 并各向异性地蚀刻金属层以沿着氧化物台面的侧壁产生位线。

53. 发明申请

US20100203727A1 METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION 有权
标题翻译：使用PITCH MULTIPLICATION的集成电路制造方法
公开(公告)号：US20100203727A1
公开(公告)日：2010-08-12
申请号：US12707560
申请日：2010-02-17
申请人： Mirzafer K. Abatchev , Gurtej Sandhu , Luan Tran , William T. Rericha , D. Mark Durcan
发明人： Mirzafer K. Abatchev , Gurtej Sandhu , Luan Tran , William T. Rericha , D. Mark Durcan
IPC分类号： H01L21/306 , H01L21/31
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.
摘要翻译：集成电路的阵列和周边中的不同尺寸的特征在单个步骤中在衬底上图案化。特别地，组合两个单独形成的图案的混合图案形成在单个掩模层上，然后转移到下面的基底。单独形成的图案中的第一个通过间距倍增形成，并且通过常规光刻形成第二个单独形成的图案。单独形成的图案中的第一个包括低于用于形成第二个单独形成的图案的光刻工艺的分辨率的线。这些线通过在光致抗蚀剂上形成图案然后将该图案刻蚀成无定形碳层而制成。在无定形碳的侧壁上形成宽度小于无定形碳的未蚀刻部分的宽度的侧壁盘。然后去除无定形碳，留下侧壁间隔物作为掩模图案。因此，间隔物形成具有小于用于在光致抗蚀剂上形成图案的光刻工艺的分辨率的特征尺寸的掩模。保护材料沉积在间隔物周围。使用硬掩模进一步保护间隔物，然后在硬掩模上形成并图案化光致抗蚀剂。光致抗蚀剂图案通过硬掩模转印到保护材料上。然后将由间隔物和临时材料制成的图案转移到下面的无定形碳硬掩模层。具有不同尺寸特征的图案然后被转移到下面的基底。

54. 发明授权

US07115525B2 Method for integrated circuit fabrication using pitch multiplication 有权
公开(公告)号：US07115525B2
公开(公告)日：2006-10-03
申请号：US10934778
申请日：2004-09-02
申请人： Mirzafer K. Abatchev , Gurtej Sandhu , Luan Tran , William T. Rericha , D. Mark Durcan
发明人： Mirzafer K. Abatchev , Gurtej Sandhu , Luan Tran , William T. Rericha , D. Mark Durcan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

55. 发明授权

US06885051B2 Minimally spaced MRAM structures 有权
标题翻译：最小间隔的MRAM结构
公开(公告)号：US06885051B2
公开(公告)日：2005-04-26
申请号：US10823553
申请日：2004-04-14
申请人： D. Mark Durcan , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
发明人： D. Mark Durcan , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
IPC分类号： H01L21/8246 , H01L27/22 , H01L31/062 , H01L31/036
CPC分类号： H01L27/222 , B82Y10/00
摘要： A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.
摘要翻译：公开了形成最小间隔的MRAM结构的方法。使用光刻技术来定义集成电路的图案，其集成电路的宽度通过蚀刻进一步减小，以允许形成用于蚀刻具有两个数字线区域中的任一个之间的最佳临界尺寸的数字线区域的图案。在最小间隔的数字区域上形成随后的MRAM结构的固定和感测层。

56. 发明授权

US06781145B2 Controlable ovonic phase-change semiconductor memory device 失效
标题翻译：可控超声相变半导体存储器件
公开(公告)号：US06781145B2
公开(公告)日：2004-08-24
申请号：US10191222
申请日：2002-07-09
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L27/10 , H01L27/105 , H01L27/24 , H01L45/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
摘要翻译：公开了一种在硫族化物存储器的电极之间具有减小的接触面积的相位相移型半导体存储器件及其形成方法。这样的存储器件通过形成从下电极元件的下表面突出的尖端而形成。在下电极上施加绝缘材料，使得尖端的上表面露出。硫族化物材料和上电极都形成在尖端顶部，或者尖端被蚀刻到绝缘材料中，并且硫族化物材料和上电极沉积在凹部内。这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

57. 发明授权

US06693319B1 Container capacitor structure and method of formation thereof 失效
标题翻译：集装箱电容器结构及其形成方法
公开(公告)号：US06693319B1
公开(公告)日：2004-02-17
申请号：US09652929
申请日：2000-08-31
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L27108
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：公开了一种容器电容器结构及其构造方法。蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

58. 发明授权

US06689661B2 Method for forming minimally spaced MRAM structures 有权
标题翻译：用于形成最小间隔MRAM结构的方法
公开(公告)号：US06689661B2
公开(公告)日：2004-02-10
申请号：US09828823
申请日：2001-04-10
申请人： D. Mark Durcan , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
发明人： D. Mark Durcan , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
IPC分类号： H01L21336
CPC分类号： H01L27/222 , B82Y10/00
摘要： A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.
摘要翻译：公开了形成最小间隔的MRAM结构的方法。使用光刻技术来定义集成电路的图案，其集成电路的宽度通过蚀刻进一步减小，以允许形成用于蚀刻具有两个数字线区域中的任一个之间的最佳临界尺寸的数字线区域的图案。在最小间隔的数字区域上形成随后的MRAM结构的固定和感测层。

59. 发明授权

US06682943B2 Method for forming minimally spaced MRAM structures 有权
标题翻译：用于形成最小间隔MRAM结构的方法
公开(公告)号：US06682943B2
公开(公告)日：2004-01-27
申请号：US09842783
申请日：2001-04-27
申请人： D. Mark Durcan , Gurtej Sandhu , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
发明人： D. Mark Durcan , Gurtej Sandhu , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
IPC分类号： H01G706
CPC分类号： H01L27/222
摘要： A method of forming minimally spaced MRAM structures is disclosed. A photolithography technique is employed to define masking patterns, on the sidewalls of which spacers are subsequently formed to reduce the distance between any of the two adjacent masking patterns. A filler material is next used to fill in the space around the masking patterns and to form filler plugs. The masking patterns and the spacers are removed using the filler plugs as a hard mask. Digit and word lines of MRAM structures are subsequently formed.
摘要翻译：公开了一种形成最小间隔MRAM结构的方法。使用光刻技术来定义掩模图案，其侧壁上随后形成间隔物以减少两个相邻掩模图案中的任一个之间的距离。填充材料接下来用于填充掩模图案周围的空间并形成填充塞。使用填充塞作为硬掩模去除掩模图案和间隔物。随后形成MRAM结构的数字和字线。

60. 发明授权

US06569727B1 Method of making a single-deposition-layer-metal dynamic random access memory 失效
标题翻译：制备单沉积层金属动态随机存取存储器的方法
公开(公告)号：US06569727B1
公开(公告)日：2003-05-27
申请号：US08852909
申请日：1997-05-08
申请人： Stephen L. Casper , Timothy J. Allen , D. Mark Durcan , Brian M. Shirley , Howard E. Rhodes
发明人： Stephen L. Casper , Timothy J. Allen , D. Mark Durcan , Brian M. Shirley , Howard E. Rhodes
IPC分类号： H01L218242
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/1815 , H01L2924/00
摘要： A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.
摘要翻译：描述了16兆比特（224）或更大密度的单沉积层金属动态随机存取存储器（DRAM）部件，其允许适用于工业标准的300ml宽SOJ（小外形J翼）封装或TSOP （薄型，小外形封装），与以前的双金属沉积分层16兆位DRAM设计相比，速度损失很少或没有速度损失。这是通过使用允许单个金属层信号路径的管芯架构来实现的，以及引线框架的新颖使用以去除芯片的大部分功率，从而允许较小的速度优化的DRAM。使用单个沉积层金属导致较低的生产成本和较短的生产时间。

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