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51. 发明申请

US20060285411A1 SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM) 有权
标题翻译：多端口动态随机存取存储器（DRAM）的单周期刷新
公开(公告)号：US20060285411A1
公开(公告)日：2006-12-21
申请号：US11160273
申请日：2005-06-16
申请人： Hoki Kim , Toshiaki Kirihata
发明人： Hoki Kim , Toshiaki Kirihata
IPC分类号： G11C7/00
CPC分类号： G11C11/4097 , G11C7/1006 , G11C7/12 , G11C7/18 , G11C8/10 , G11C8/16 , G11C11/406 , G11C11/40603 , G11C11/4094
摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.
摘要翻译：具有与正常读取和写入操作交织的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

52. 发明授权

US07145829B1 Single cycle refresh of multi-port dynamic random access memory (DRAM) 有权
标题翻译：多端口动态随机存取存储器（DRAM）的单周期刷新
公开(公告)号：US07145829B1
公开(公告)日：2006-12-05
申请号：US11160273
申请日：2005-06-16
申请人： Hoki Kim , Toshiaki Kirihata
发明人： Hoki Kim , Toshiaki Kirihata
IPC分类号： C11C7/00
CPC分类号： G11C11/4097 , G11C7/1006 , G11C7/12 , G11C7/18 , G11C8/10 , G11C8/16 , G11C11/406 , G11C11/40603 , G11C11/4094
摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.
摘要翻译：具有与正常读取和写入操作交错的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

53. 发明授权

US06683486B2 Low voltage shifter with latching function 失效
标题翻译：具有锁定功能的低电压转换器
公开(公告)号：US06683486B2
公开(公告)日：2004-01-27
申请号：US10114221
申请日：2002-04-02
申请人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
发明人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
IPC分类号： H03L500
CPC分类号： H03K3/356147 , H03K3/012
摘要： A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.
摘要翻译：具有嵌入式锁存器的低电压电平移位器电路，其在具有低电压信号的信号线上实现。包括低电压电平移位器电路，其配置为从信号线的第一部分接收低电压输入信号，并在信号线的第二部分上输出更高电压的输出信号。还包括锁存电路，并且被配置为锁存来自信号线的第一部分的低电压输入信号。

54. 发明授权

US06404689B1 Method and structure for hiding a refresh operation in a DRAM having an interlocked pipeline 失效
标题翻译：在具有互锁管道的DRAM中隐藏刷新操作的方法和结构
公开(公告)号：US06404689B1
公开(公告)日：2002-06-11
申请号：US09822430
申请日：2001-03-30
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Chorng-Lii Hwang
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Chorng-Lii Hwang
IPC分类号： G11C700
CPC分类号： G11C7/1039 , G11C7/1072 , G11C11/406
摘要： Hiding a refresh operation in a DRAM or eDRAM is achieved by tailoring an external random access time tRCext to slightly extend into the internal random access cycle time. This allows for an additional internal random access cycle time tRCint after a plurality of external random access cycles n(tRCext) when enabling the corresponding internal random access operation n(tRCint). The additional core random access cycle time tRCint is achieved at every nth clock, where n>tRCint/(tRCext−tRCint), or at a time defined by the product of tRCext and tRCint/(tRCext−tRCint). The additional core cycle time tRCint is used for refreshing the DRAM By scheduling a refresh-to-refresh period equal to or greater than the phase recovery time, a fully command compatible static random access time can be realized with DRAM cells.
摘要翻译：在DRAM或eDRAM中隐藏刷新操作是通过调整外部随机访问时间tRCext来略微延伸到内部随机访问周期中实现的。这允许在启用相应的内部随机访问操作n（tRCint）之后的多个外部随机访问周期n（tRCext）之后的额外的内部随机访问周期时间tRCint。在第n个时钟，其中n> tRCint /（tRCext-tRCint），或由tRCext和tRCint /（tRCext-tRCint）的乘积定义的时间，实现了额外的核随机访问周期时间tRCint。附加核心周期时间tRCint用于刷新DRAM通过调度等于或大于相位恢复时间的刷新刷新周期，可以使用DRAM单元实现完全命令兼容的静态随机存取时间。

55. 发明授权

US06370055B1 Semiconductor memory having asymmetric column addressing and twisted read write drive (RWD) line architecture 失效
标题翻译：具有非对称列寻址和双绞读写驱动（RWD）线架构的半导体存储器
公开(公告)号：US06370055B1
公开(公告)日：2002-04-09
申请号：US09795761
申请日：2001-02-28
申请人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
发明人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G11C506
CPC分类号： G11C5/063
摘要： There is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns is included in each of the plurality of memory units. Each of the plurality of columns is adapted to access the plurality of RWD lines through asymmetrical addressing.
摘要翻译：提供了具有多个存储单元的半导体存储器。存储器包括水平和/或垂直扭转的多个读写驱动（RWD）线，使得RWD线在多个存储器单元之间共享。在多个存储单元的每一个中包括多个列。多个列中的每一个适于通过非对称寻址来访问多个RWD线。

56. 发明授权

US06288436B1 Mixed fuse technologies 失效
标题翻译：混合保险丝技术
公开(公告)号：US06288436B1
公开(公告)日：2001-09-11
申请号：US09361960
申请日：1999-07-27
申请人： Chandrasekhar Narayan , Kenneth Arndt , Toshiaki Kirihata , David Lachtrupp , Axel Brintzinger , Gabriel Daniel
发明人： Chandrasekhar Narayan , Kenneth Arndt , Toshiaki Kirihata , David Lachtrupp , Axel Brintzinger , Gabriel Daniel
IPC分类号： H01L2900
CPC分类号： H01L22/22 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.
摘要翻译：多种不同类型的保险丝，每种类型的用于特定用途的保险丝都位于半导体集成电路晶片上，其中激活一种类型的保险丝不会使不同类型的保险丝失效。第一种类型的保险丝，例如激光激活的保险丝，主要用于修复晶圆级的缺陷，而第二种类型的保险丝，例如电激活保险丝，用于修复将IC芯片安装在模块上所发现的缺陷并在老化测试中强调模块。模块级别的缺陷通常是单电池故障，它们由电气编程的保险丝固化，以激活模块级冗余。

57. 发明授权

US06262615B1 Dynamic logic circuit 有权
标题翻译：动态逻辑电路
公开(公告)号：US06262615B1
公开(公告)日：2001-07-17
申请号：US09257304
申请日：1999-02-25
申请人： Toshiaki Kirihata , Gerd Frankowsky
发明人： Toshiaki Kirihata , Gerd Frankowsky
IPC分类号： H03K3037
CPC分类号： G11C19/28 , G11C7/1048 , G11C19/00 , H03K19/0963
摘要： A dynamic logic circuit having a charging circuit, comprising a first transistor having a first source/drain electrode adapted for coupling to a voltage supply and a second source/drain electrode connected to a node. The charging circuit couples the voltage supply to the node to place an initial charge on the node. A data transfer circuit is provided comprising a second transistor having a gate adapted for coupling to an input strobe pulse, a first source/drain electrode connected to the node, and a second source/drain electrode responsive to an input data and the input strobe pulse, for transferring the input data to the node to the node such that the pre-charged node is either discharged or remains depending on the input data. An output circuit is responsive to an output strobe pulse for coupling the data at the node to an output. A trailing edge detector of the output strobe pulse detects a time at which the coupling of the data to the output is complete and pre-charges the node at a high level for a subsequent input strobe pulse.
摘要翻译：一种具有充电电路的动态逻辑电路，包括具有适于耦合到电压源的第一源极/漏极电极和连接到节点的第二源极/漏极电极的第一晶体管。充电电路将电压源耦合到节点以在节点上放置初始电荷。提供了一种数据传输电路，包括具有适于耦合到输入选通脉冲的栅极的第二晶体管，连接到该节点的第一源极/漏极电极和响应于输入数据和输入选通脉冲的第二源极/漏极电极用于将输入数据传送到节点到节点，使得预充电节点根据输入数据被放电或保持。输出电路响应于输出选通脉冲，用于将节点处的数据耦合到输出。输出选通脉冲的后沿检测器检测数据到输出的耦合完成的时间，并且为了后续的输入选通脉冲将节点预充电到高电平。

58. 发明授权

US06240043B1 SDRAM with a maskable input 有权
标题翻译： SDRAM具有可屏蔽输入
公开(公告)号：US06240043B1
公开(公告)日：2001-05-29
申请号：US09456588
申请日：1999-12-08
申请人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
发明人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
IPC分类号： G11C800
CPC分类号： G11C7/1006 , G11C7/1021
摘要： A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.
摘要翻译：包括在集成电路中的随机存取存储器（RAM），特别是具有可屏蔽数据输入的同步动态RAM（SDRAM）。 SDRAM包括一个xy数据输入寄存器，它接收与数据线（DQ）数量相对应的突发x位长和y位宽。 xy屏蔽寄存器接收每个接收数据位的相应掩码位，每个掩码位指示对应的数据位是否存储在SDRAM阵列中。使能缓冲器从xy数据输入寄存器接收数据输出，并根据存储在xy掩码寄存器中的相应屏蔽状态将各个数据输出传递给阵列。掩模寄存器优选设置为掩蔽状态。当使能信号被逐位置信时，会发生解掩码。当允许写突发中断命令被断言时，允许脉冲串长度内的其余位处于屏蔽状态。在输入预取期间，可能会发生中断，导致突发或预取的任何接收的部分被存储在阵列中，而不会干扰对应于预取的余额或剩余比特的存储器位置。

59. 发明授权

US06230290B1 Method of self programmed built in self test 失效
标题翻译：自我编程内置自检方法
公开(公告)号：US06230290B1
公开(公告)日：2001-05-08
申请号：US08887462
申请日：1997-07-02
申请人： David F. Heidel , Wei Hwang , Toshiaki Kirihata
发明人： David F. Heidel , Wei Hwang , Toshiaki Kirihata
IPC分类号： G11C2900
CPC分类号： G11C29/16
摘要： A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.
摘要翻译：一种用于存储器（例如，动态随机存取存储器（DRAM））的自编程内置自检（BIST）的方法。可以是DRAM芯片的DRAM包括DRAM内核，微代码或初始命令ROM，BIST引擎，命令寄存器和自编程电路。在自检期间，BIST引擎可以正常测试DRAM，直到遇到错误。当遇到错误时，自编程电路在较不严格的条件下重新启动自检程序。可选地，当DRAM测试无错误时，自编程电路可以在更严格的条件下重新开始测试以确定DRAM功能限制。

60. 发明授权

US06185712B2 Chip performance optimization with self programmed built in self test 失效
标题翻译：芯片性能优化与自编程内置自检
公开(公告)号：US06185712B2
公开(公告)日：2001-02-06
申请号：US09109145
申请日：1998-07-02
申请人： Toshiaki Kirihata , Christopher Douglas Wait
发明人： Toshiaki Kirihata , Christopher Douglas Wait
IPC分类号： G01R3128
CPC分类号： G11C29/026 , G11C7/20 , G11C11/401 , G11C11/4072 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2029/5004 , G11C2207/2254
摘要： An integrated circuit (IC) chip wherein a built-in self test determines the IC's optimum electrical performance. A corresponding optimum performance setting is stored in NVRAM on the chip. Upon each chip power-up, the optimum performance setting is retrieved and provided to chip control which sets the chip for its best performance.
摘要翻译：集成电路（IC）芯片，其中内置的自检确定了IC的最佳电气性能。相应的最佳性能设置存储在芯片的NVRAM中。在每个芯片上电时，检索最佳性能设置并将其提供给芯片控制，从而使芯片达到最佳性能。

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