专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08416624B2 Erase and programming techniques to reduce the widening of state distributions in non-volatile memories 有权
标题翻译：擦除和编程技术来减少非易失性存储器中状态分布的扩大
公开(公告)号：US08416624B2
公开(公告)日：2013-04-09
申请号：US13072387
申请日：2011-03-25
申请人： Bo Lei , Guirong Liang , Anubhav Khandelwal , Jun Wan
发明人： Bo Lei , Guirong Liang , Anubhav Khandelwal , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/3404
摘要： Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.
摘要翻译：提供了用于存储器件的技术，以通过减少在多个写入/擦除周期之后发生的状态分布的扩大来提高可靠性和耐久性。一组技术使用预处理操作，其中可以包括程序和温和擦除的脉冲序列被施加到一个或多个字线，同时在字线方向，位线方向或两者上施加电压差。另一组技术使用双脉冲或多脉冲程序过程，其中在一对的第一脉冲中使用增加的字线对字线差分。

52. 发明授权

US08145855B2 Built in on-chip data scrambler for non-volatile memory 有权
标题翻译：内置片上数据扰频器，用于非易失性存储器
公开(公告)号：US08145855B2
公开(公告)日：2012-03-27
申请号：US12209708
申请日：2008-09-12
申请人： Jun Wan , Yupin K. Fong , Man L. Mui
发明人： Jun Wan , Yupin K. Fong , Man L. Mui
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F2212/1032
摘要： A non-volatile memory in which data is randomized before being stored in the non-volatile memory to minimize data pattern-related read failures. Randomizing is performed using circuitry on the memory die so that the memory die is portable relative to an external, off-chip controller. Circuitry on the memory die scrambles user data based on a key which is generated using a seed which is shifted according to a write address. Corresponding on-chip descrambling is also provided.
摘要翻译：一种非易失性存储器，其中数据在被存储在非易失性存储器中之前被随机化以最小化与数据模式相关的读取故障。使用存储器管芯上的电路执行随机化，使得存储器管芯相对于外部的片外控制器是便携式的。存储器上的电路根据使用根据写入地址移位的种子生成的密钥对用户数据进行加扰。还提供了相应的片上解扰。

53. 发明授权

US08036044B2 Dynamically adjustable erase and program levels for non-volatile memory 有权
标题翻译：用于非易失性存储器的动态可调擦除和程序级别
公开(公告)号：US08036044B2
公开(公告)日：2011-10-11
申请号：US12504576
申请日：2009-07-16
申请人： Yingda Dong , Jun Wan
发明人： Yingda Dong , Jun Wan
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/344 , G11C16/16
摘要： Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided.
摘要翻译：通过自适应地调整擦除验证级别和程序验证级别来降低非易失性存储元件的降级。确定完成擦除操作所需的擦除脉冲数或最高擦除脉冲幅度。当数字或幅度达到极限时，擦除验证电平增加。随着擦除验证电平的增加，所需擦除脉冲的数量减少，因为擦除操作可以更容易地完成。从而避免了退化的加速增加。一个或多个程序验证级别也可以随着擦除验证级别的变化而增加。一个或多个程序验证电平可以增加与擦除验证电平相同的增量，以在擦除状态和编程状态之间维持恒定的阈值电压窗口，或者通过不同的增量。提供了具有二进制或多级存储元素的实现。

54. 发明授权

US07606074B2 Word line compensation in non-volatile memory erase operations 有权
标题翻译：非易失性存储器擦除操作中的字线补偿
公开(公告)号：US07606074B2
公开(公告)日：2009-10-20
申请号：US12242831
申请日：2008-09-30
申请人： Jun Wan , Jeffrey W Lutze , Chan-Sui Pang
发明人： Jun Wan , Jeffrey W Lutze , Chan-Sui Pang
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/16 , G11C16/3468
摘要： Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.
摘要翻译：在擦除操作期间，补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。补偿电压可以补偿与其他存储器单元和/或选择栅极的NAND串的存储器单元电容耦合的电压。补偿电压可以施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。还可以将补偿电压施加到内部存储器单元，以使其与端部存储器单元的擦除行为相等。此外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。可以使用各种补偿电压。

55. 发明授权

US07577034B2 Reducing programming voltage differential nonlinearity in non-volatile storage 有权
标题翻译：降低非易失性存储器中的编程电压差分非线性
公开(公告)号：US07577034B2
公开(公告)日：2009-08-18
申请号：US11861909
申请日：2007-09-26
申请人： Dana Lee , Jun Wan
发明人： Dana Lee , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C29/00
摘要： A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which provides the program voltages can have a nonlinear output, such as when certain code words are input to the DAC. The memory device can be tested beforehand to determine where the nonlinearities occur, and configured to take corrective action when the corresponding code words are input. For example, the DAC may have a nonlinear output when a rollover code word is input, e.g., a when a string of least significant bits in successive code words change from 1's to 0's. The corrective action can include repeating a prior program pulse or adjusting a duration of a program pulse.
摘要翻译：采取校正动作来调整应用于存储器件中的选定字线的编程电压中的非线性。非线性导致不均匀的程序电压步长，这可能导致过度编程或缓慢编程。提供程序电压的数模转换器（DAC）可以具有非线性输出，例如当某些代码字被输入到DAC时。可以预先测试存储器件以确定非线性发生的位置，并且配置为在输入相应的代码字时采取校正动作。例如，当输入翻转代码字时，DAC可以具有非线性输出，例如，当连续代码字中的最低有效位的串从1变为0时。校正动作可以包括重复先前的编程脉冲或调整编程脉冲的持续时间。

56. 发明申请

US20090083007A1 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING WALL THICKNESS IN GRAPHIC MODEL 审中-公开
标题翻译：用于确定图形模型中的壁厚的系统，方法和计算机程序产品
公开(公告)号：US20090083007A1
公开(公告)日：2009-03-26
申请号：US12237193
申请日：2008-09-24
申请人： Jun Wan , Chee-Keong Chong , Zhi Li
发明人： Jun Wan , Chee-Keong Chong , Zhi Li
IPC分类号： G06F17/50
CPC分类号： G06T17/20 , G06F17/5018
摘要： A system, method, and computer program product for measuring wall thickness. After an internal body topology of the model is generated, the topology is traversed between wall elements to determine wall thickness.
摘要翻译：一种用于测量壁厚的系统，方法和计算机程序产品。在生成模型的内部结构拓扑之后，在壁元素之间遍历拓扑以确定壁厚。

57. 发明申请

US20090021983A1 Word Line Compensation In Non-Volatile Memory Erase Operations 有权
标题翻译：非易失性存储器擦除操作中的字线补偿
公开(公告)号：US20090021983A1
公开(公告)日：2009-01-22
申请号：US12242831
申请日：2008-09-30
申请人： Jun Wan , Jeffrey W. Lutze , Chan-Sui Pang
发明人： Jun Wan , Jeffrey W. Lutze , Chan-Sui Pang
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/16 , G11C16/3468
摘要： Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.
摘要翻译：在擦除操作期间，补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。补偿电压可以补偿与其他存储器单元和/或选择栅极的NAND串的存储器单元电容耦合的电压。补偿电压可以施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。还可以将补偿电压施加到内部存储器单元，以将其擦除行为与端部存储器单元相等。此外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。可以使用各种补偿电压。

58. 发明授权

US07463532B2 Comprehensive erase verification for non-volatile memory 有权
标题翻译：非易失性存储器的全面擦除验证
公开(公告)号：US07463532B2
公开(公告)日：2008-12-09
申请号：US11316119
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

59. 发明授权

US07450433B2 Word line compensation in non-volatile memory erase operations 有权
标题翻译：非易失性存储器擦除操作中的字线补偿
公开(公告)号：US07450433B2
公开(公告)日：2008-11-11
申请号：US11025620
申请日：2004-12-29
申请人： Jun Wan , Jeffrey W. Lutze , Chan-Sui Pang
发明人： Jun Wan , Jeffrey W. Lutze , Chan-Sui Pang
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/16 , G11C16/3468
摘要： Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.
摘要翻译：在擦除操作期间，补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。补偿电压可以补偿与其他存储器单元和/或选择栅极的NAND串的存储器单元电容耦合的电压。补偿电压可以施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。还可以将补偿电压施加到内部存储器单元，以使其与端部存储器单元的擦除行为相等。此外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。可以使用各种补偿电压。

60. 发明授权

US07254071B2 Flash memory devices with trimmed analog voltages 有权
标题翻译：具有微调模拟电压的闪存设备
公开(公告)号：US07254071B2
公开(公告)日：2007-08-07
申请号：US11332567
申请日：2006-01-12
申请人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
发明人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
IPC分类号： G11C29/00
CPC分类号： G11C16/0483 , G11C7/16 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C27/005 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C2029/5004 , G11C2211/5621 , G11C2211/5634
摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.
摘要翻译：公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值它提供了选择用于正常操作的最接近的结果。这些DAC取决于我也被修剪的参考源的值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式