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51. 发明申请

US20100264484A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100264484A1
公开(公告)日：2010-10-21
申请号：US12761012
申请日：2010-04-15
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： H01L27/088
CPC分类号： H01L21/84 , H01L21/823828 , H01L21/823878 , H01L21/823885 , H01L27/092 , H01L27/1203 , H01L29/78642
摘要： In a vertical transistor comprising a pillar-shaped semiconductor layer and a gate electrode formed to around the pillar-shaped semiconductor layer, it is difficult to form a transistor having a gate length greater than that of the vertical transistor. The present invention provides a semiconductor device which comprises two vertical transistors comprising first and second pillar-shaped semiconductor layers each formed on a first diffusion layer on a substrate. The vertical transistors have a common gate electrode. A first upper diffusion layer formed on a top of the first pillar-shaped semiconductor layer is connected to a source electrode, and a second upper diffusion layer formed on a top of the second pillar-shaped semiconductor layer is connected to a drain electrode. The vertical transistors are connected in series to operate as a composite transistor having a gate length two times greater than that of each of the vertical transistors.
摘要翻译：在包括柱状半导体层和形成在柱状半导体层周围的栅电极的垂直晶体管中，难以形成栅极长度大于垂直晶体管的栅极长度的晶体管。本发明提供一种半导体器件，其包括两个垂直晶体管，其包括分别形成在衬底上的第一扩散层上的第一和第二柱状半导体层。垂直晶体管具有公共栅电极。形成在第一柱状半导体层的顶部的第一上部扩散层与源极连接，形成在第二柱状半导体层的顶部的第二上部扩散层与漏极连接。垂直晶体管串联连接以作为具有比每个垂直晶体管的栅极长度大两倍的栅极长度的复合晶体管工作。

52. 发明申请

US20100207201A1 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR 有权
标题翻译：半导体器件及其生产方法
公开(公告)号：US20100207201A1
公开(公告)日：2010-08-19
申请号：US12704935
申请日：2010-02-12
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823885 , H01L21/823487 , H01L21/823828 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42356 , H01L29/456 , H01L29/66666 , H01L29/7827 , H01L29/7843
摘要： It is intended to provide a semiconductor device comprising a circuit which has a connection between one of a drain region and a source region of a first MOS transistor and one of a drain region and a source region of a second MOS transistor. The semiconductor device comprises: a substrate; a dielectric film on the substrate; and a planar semiconductor layer formed on the on-substrate dielectric film, wherein: the first MOS transistor includes a first drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a second source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed in such a manner that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer through a first dielectric film; and the second MOS transistor includes a third drain or source region formed in the planar semiconductor layer, a second pillar-shaped semiconductor layer formed on the planar semiconductor layer, a fourth source or drain region formed in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode formed in such a manner that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer through a second dielectric film, and wherein a first silicide layer is formed to connect at least a part of a surface of the first drain or source region and at least a part of a surface of the third drain or source region, wherein the first silicide layer is formed in an area other than an area in which a contact for at least the first drain or source region and the third drain or source region is formed.
摘要翻译：旨在提供一种半导体器件，其包括在第一MOS晶体管的漏极区域和源极区域之一与第二MOS晶体管的漏极区域和源极区域中的一个之间具有连接的电路。半导体器件包括：衬底; 基板上的电介质膜; 以及形成在所述基板上电介质膜上的平面状半导体层，其中：所述第一MOS晶体管包括形成在所述平面状半导体层中的第一漏极或源极区域，形成在所述平面状半导体层上的第一柱状半导体层，源极或漏极区域形成在第一柱状半导体层的上部，以及第一栅极电极，其形成为使得第一栅电极通过第一电介质膜包围第一柱状半导体层的侧壁; 并且所述第二MOS晶体管包括形成在所述平面半导体层中的第三漏极或源极区域，形成在所述平面半导体层上的第二柱状半导体层，形成在所述第二柱状半导体层的上部的第四源极或漏极区域半导体层和第二栅电极，其形成为使得第二栅电极通过第二电介质膜包围第二柱状半导体层的侧壁，并且其中形成第一硅化物层以将至少一部分所述第一漏极或源极区域的表面和所述第三漏极或源极区域的表面的至少一部分，其中所述第一硅化物层形成在除了至少第一漏极或第二漏极或源极区域的接触区域之外的区域中，源极区域和第三漏极或源极区域。

53. 发明授权

US08598650B2 Semiconductor device and production method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08598650B2
公开(公告)日：2013-12-03
申请号：US12704935
申请日：2010-02-12
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： H01L25/04
CPC分类号： H01L21/823885 , H01L21/823487 , H01L21/823828 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42356 , H01L29/456 , H01L29/66666 , H01L29/7827 , H01L29/7843
摘要： It is intended to provide a semiconductor device comprising a circuit which has a connection between a drain region or a source region of a first MOS transistor and a drain region or a source region of a second MOS transistor. Each surround gate transistor (SGT) has a gate electrode that surrounds a sidewall of a pillar-shaped semiconductor layer.
摘要翻译：旨在提供一种半导体器件，其包括在第一MOS晶体管的漏极区域或源极区域与第二MOS晶体管的漏极区域或源极区域之间具有连接的电路。每个环绕栅极晶体管（SGT）具有围绕柱状半导体层的侧壁的栅电极。

54. 发明授权

US08248876B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08248876B2
公开(公告)日：2012-08-21
申请号：US13208844
申请日：2011-08-12
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： G11C7/02
CPC分类号： H01L27/10885 , G11C11/4023 , H01L27/0207 , H01L27/10823 , H01L27/10876
摘要： In a 4F2 memory cell designed using an SGT as a vertical transistor, a bit line has a high resistance because it is comprised of a diffusion layer underneath a pillar-shaped silicon layer, which causes a problem of slowdown in memory operation speed. The present invention provides a semiconductor storage device comprising an SGT-based 4F2 memory cell, wherein a bit line-backing cell having the same structure as that of a memory cell is inserted into a memory cell array to allow a first bit line composed of a diffusion layer to be backed with a low-resistance second bit line through the bit line backing cell, so as to provide a substantially low-resistance bit line, while suppressing an increase in area of the memory cell array.
摘要翻译：在使用SGT作为垂直晶体管设计的4F2存储单元中，位线具有高电阻，因为它由柱状硅层下面的扩散层组成，这导致存储器操作速度降低的问题。本发明提供了一种包括基于SGT的4F2存储单元的半导体存储装置，其中具有与存储单元相同结构的位线支持单元插入到存储单元阵列中，以允许由扩散层通过位线背衬单元通过低电阻第二位线支持，从而在抑制存储单元阵列的面积的增加的同时提供基本上较低的电阻位线。

55. 发明申请

US20120181622A1 SEMICONDUCTOR SURROUND GATE SRAM STORAGE DEVICE 审中-公开
标题翻译： SEMICONDUCTOR SURRIDE GATE SRAM存储器件
公开(公告)号：US20120181622A1
公开(公告)日：2012-07-19
申请号：US13417967
申请日：2012-03-12
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： H01L27/11
CPC分类号： H01L27/1112 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/0207 , H01L27/088 , H01L27/11 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer, and each of the load resistor elements is made of polysilicon and formed on the planar silicon layer.
摘要翻译：旨在在包括垂直晶体管SGT的E / R型4T-SRAM中实现足够小的SRAM单元面积和稳定的操作裕度。在使用四个MOS晶体管和两个负载电阻元件构成的静态存储单元中，构成存储单元的各MOS晶体管形成在形成于掩埋氧化膜上的平面硅层上，具有漏极，栅极和源极沿垂直方向布置，其中栅极形成为围绕柱状半导体层，并且每个负载电阻器元件由多晶硅制成并形成在平面硅层上。

56. 发明授权

US08212311B2 Semiconductor device having increased gate length implemented by surround gate transistor arrangements 有权
标题翻译：具有由环绕栅极晶体管布置实现的具有增加的栅极长度的半导体器件
公开(公告)号：US08212311B2
公开(公告)日：2012-07-03
申请号：US12761012
申请日：2010-04-15
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： H01L27/088
CPC分类号： H01L21/84 , H01L21/823828 , H01L21/823878 , H01L21/823885 , H01L27/092 , H01L27/1203 , H01L29/78642
摘要： In a vertical transistor comprising a pillar-shaped semiconductor layer and a gate electrode formed around the pillar-shaped semiconductor layer, it is difficult to form a transistor having a gate length greater than that of the vertical transistor. The present invention provides a semiconductor device which comprises two vertical transistors comprising first and second pillar-shaped semiconductor layers each formed on a first diffusion layer on a substrate. The vertical transistors have a common gate electrode. A first upper diffusion layer formed on a top of the first pillar-shaped semiconductor layer is connected to a source electrode, and a second upper diffusion layer formed on a top of the second pillar-shaped semiconductor layer is connected to a drain electrode. The vertical transistors are connected in series to operate as a composite transistor having a gate length two times greater than that of each of the vertical transistors.
摘要翻译：在包括柱状半导体层和形成在柱状半导体层周围的栅电极的垂直晶体管中，难以形成栅极长度大于垂直晶体管的栅极长度的晶体管。本发明提供一种半导体器件，其包括两个垂直晶体管，其包括分别形成在衬底上的第一扩散层上的第一和第二柱状半导体层。垂直晶体管具有公共栅电极。形成在第一柱状半导体层的顶部的第一上部扩散层与源极连接，形成在第二柱状半导体层的顶部的第二上部扩散层与漏极连接。垂直晶体管串联连接以作为具有比每个垂直晶体管的栅极长度大两倍的栅极长度的复合晶体管工作。

57. 发明授权

US08154086B2 Semiconductor surround gate SRAM storage device 有权
标题翻译：半导体环绕门SRAM存储器件
公开(公告)号：US08154086B2
公开(公告)日：2012-04-10
申请号：US12703968
申请日：2010-02-11
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1112 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/0207 , H01L27/088 , H01L27/11 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer, and each of the load resistor elements is made of polysilicon and formed on the planar silicon layer.
摘要翻译：旨在在包括垂直晶体管SGT的E / R型4T-SRAM中实现足够小的SRAM单元面积和稳定的操作裕度。在使用四个MOS晶体管和两个负载电阻元件构成的静态存储单元中，构成存储单元的各MOS晶体管形成在形成于掩埋氧化膜上的平面硅层上，具有漏极，栅极和源极沿垂直方向布置，其中栅极形成为围绕柱状半导体层，并且每个负载电阻器元件由多晶硅制成并形成在平面硅层上。

58. 发明授权

US08023352B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08023352B2
公开(公告)日：2011-09-20
申请号：US12702719
申请日：2010-02-09
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： G11C11/02
CPC分类号： H01L27/10885 , G11C11/4023 , H01L27/0207 , H01L27/10823 , H01L27/10876
摘要： In a 4F2 memory cell designed using an SGT as a vertical transistor, a bit line has a high resistance because it is comprised of a diffusion layer underneath a pillar-shaped silicon layer, which causes a problem of slowdown in memory operation speed. The present invention provides a semiconductor storage device comprising an SGT-based 4F2 memory cell, wherein a bit line-backing cell having the same structure as that of a memory cell is inserted into a memory cell array to allow a first bit line composed of a diffusion layer to be backed with a low-resistance second bit line through the bit line backing cell, so as to provide a substantially low-resistance bit line, while suppressing an increase in area of the memory cell array.
摘要翻译：在使用SGT作为垂直晶体管设计的4F2存储单元中，位线具有高电阻，因为它由柱状硅层下面的扩散层组成，这导致存储器操作速度降低的问题。本发明提供了一种包括基于SGT的4F2存储单元的半导体存储装置，其中具有与存储单元相同结构的位线支持单元插入到存储单元阵列中，以允许由扩散层通过位线背衬单元通过低电阻第二位线支持，从而在抑制存储单元阵列的面积的增加的同时提供基本上较低的电阻位线。

59. 发明申请

US20110062529A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110062529A1
公开(公告)日：2011-03-17
申请号：US12882847
申请日：2010-09-15
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： H01L27/092
CPC分类号： H01L29/7827 , H01L27/0207 , H01L27/11 , H01L27/1112 , H01L28/20
摘要： In a static memory cell configured using four MOS transistors and two load resistance elements, the MOS transistors are formed on diffusion layers formed on a substrate. The diffusion layers serve as memory nodes. The drain, gate and source of the MOS transistors are arranged in the direction orthogonal to the substrate, and the gate surrounds a columnar semiconductor layer. In addition, the load resistance elements are formed by contact plugs. In this way, it is possible to form a SRAM cell with a small area.
摘要翻译：在使用四个MOS晶体管和两个负载电阻元件配置的静态存储单元中，MOS晶体管形成在形成在基板上的扩散层上。扩散层用作存储器节点。 MOS晶体管的漏极，栅极和源极沿与衬底正交的方向排列，栅极围绕柱状半导体层。此外，负载电阻元件由接触插塞形成。以这种方式，可以形成具有小面积的SRAM单元。

60. 发明申请

US20100219482A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100219482A1
公开(公告)日：2010-09-02
申请号：US12699634
申请日：2010-02-03
申请人： Fujio Masuoka , Shintaro Arai
发明人： Fujio Masuoka , Shintaro Arai
IPC分类号： H01L29/78
CPC分类号： H01L27/1112 , H01L21/84 , H01L27/0207 , H01L27/11 , H01L27/1203 , H01L29/78642
摘要： It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a Loadless 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area.
摘要翻译：旨在在包括垂直晶体管SGT的无负载4T-SRAM中实现足够小的SRAM单元面积和稳定的操作余量。在使用四个MOS晶体管构成的静态存储单元中，构成存储单元的MOS晶体管形成在形成于掩埋氧化膜上的平面硅层上，具有漏极，栅极和源极的结构沿垂直方向布置，其中所述栅极形成为围绕柱状半导体层。平面硅层包括具有第一导电类型的第一有源区和具有第二导电类型的第二有源区。第一和第二有源区域通过形成在平面硅层的表面中的硅化物层彼此连接，以实现具有足够小的面积的SRAM单元。

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