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51. 发明授权

US07906439B2 Method of fabricating a MEMS/NEMS electromechanical component 有权
标题翻译：制造MEMS / NEMS机电元件的方法
公开(公告)号：US07906439B2
公开(公告)日：2011-03-15
申请号：US12488898
申请日：2009-06-22
申请人： François Perruchot , Bernard Diem , Vincent Larrey , Laurent Clavelier , Emmanuel Defay
发明人： François Perruchot , Bernard Diem , Vincent Larrey , Laurent Clavelier , Emmanuel Defay
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： B81C1/00507 , B81B2201/0271 , B81C2201/0115 , B81C2201/0136 , B81C2201/0177 , B81C2203/0136 , B81C2203/0145 , H03H3/0072 , H03H9/175 , H03H9/2436 , Y10S438/933
摘要： The invention provides a method of fabricating and electromechanical device having an active element on at least one substrate, the method having the steps of: a) making a heterogeneous substrate having a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at least a portion of the second region between said cavity and said interface layer; wherein the first and second portions of the substrate are constituted respectively from first and second substrates that are assembled together by bonding, at least one of them including at least one said interface layer over at least a fraction of its surface.
摘要翻译：本发明提供一种在至少一个基板上具有有源元件的制造方法和机电装置，该方法具有以下步骤：a）制造具有第一部分，界面层和第二部分的非均相基底，第一部分包括夹在形成于第一单晶材料中的第一和第二区域之间的一个或多个掩埋区域，第一区域延伸到第一部分的表面，第二区域延伸到界面层，至少一个所述掩埋区域至少部分地由第二单晶材料制成，以使其相对于第一和第二区域选择性地具有攻击性; b）从所述第一部分的表面和所述第一区域制造开口，所述第一区域开放到至少一个所述掩埋区域; 以及c）蚀刻至少一个掩埋区域的至少一部分以形成至少一个空腔，以便限定至少一个有源元件，所述至少一个有源元件是所述腔和所述界面层之间的第二区域的至少一部分; 其中所述基板的第一和第二部分分别由通过粘接而组装在一起的第一和第二基板构成，其中至少一个在其表面的至少一部分上包括至少一个所述界面层。

52. 发明申请

US20100244197A1 EPITAXIAL METHODS AND STRUCTURES FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS 失效
标题翻译：用于减少半导体材料表面偏离密度的外延方法和结构
公开(公告)号：US20100244197A1
公开(公告)日：2010-09-30
申请号：US12721461
申请日：2010-03-10
申请人： Chantal Arena , Laurent Clavelier , Marc Rabarot
发明人： Chantal Arena , Laurent Clavelier , Marc Rabarot
IPC分类号： H01L29/20 , H01L21/302
CPC分类号： H01L29/2003 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639
摘要： The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.
摘要翻译：本发明提供了用于减少半导体层的表面位错的方法和结构，并且可以在半导体结构和包含III族氮化物材料的层的外延生长期间使用。实施例涉及形成多个位错坑塞，以防止位错从材料的下层扩散到随后的材料半导体层中。

53. 发明授权

US07732282B2 Transistor of the I-MOS type comprising two independent gates and method of using such a transistor 有权
标题翻译：包括两个独立栅极的I-MOS型晶体管和使用这种晶体管的方法
公开(公告)号：US07732282B2
公开(公告)日：2010-06-08
申请号：US12085866
申请日：2006-12-01
申请人： Cyrille Le Royer , Olivier Faynot , Laurent Clavelier
发明人： Cyrille Le Royer , Olivier Faynot , Laurent Clavelier
IPC分类号： H01L21/00
CPC分类号： H01L27/1057 , H01L29/7391
摘要： The transistor comprises a source and a drain separated by a lightly doped intermediate zone. The intermediate zone forms first and second junctions respectively with the source and with the drain. The transistor comprises a first gate to generate an electric field in the intermediate zone, on the same side as the first junction, and a second gate to generate an electric field in the intermediate zone, on the same side as the second junction.
摘要翻译：晶体管包括由轻掺杂的中间区分隔开的源极和漏极。中间区域分别与源极和漏极形成第一和第二结。所述晶体管包括第一栅极，用于在与所述第一接合部相同的一侧产生所述中间区域中的电场，以及在与所述第二接合部相同的一侧在所述中间区域中产生电场的第二栅极。

54. 发明申请

US20090321887A1 METHOD OF FABRICATING AN ELECTROMECHANICAL STRUCTURE INCLUDING AT LEAST ONE MECHANICAL REINFORCING PILLAR 审中-公开
标题翻译：制造一个机械结构的机械结构的方法，包括一个机械增强支柱
公开(公告)号：US20090321887A1
公开(公告)日：2009-12-31
申请号：US12488841
申请日：2009-06-22
申请人： Vincent Larrey , François Perruchot , Bernard Diem , Laurent Clavelier , Philippe Robert
发明人： Vincent Larrey , François Perruchot , Bernard Diem , Laurent Clavelier , Philippe Robert
IPC分类号： H01L21/30 , H01L23/58
CPC分类号： H01L29/66007 , B81B2201/0264 , B81C1/00357 , B81C1/00682 , B81C2201/019 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method of fabricating an electromechanical structure presenting a first substrate (1) including at least one layer (1′) of monocrystalline material covered in a sacrificial layer (2) that presents a free surface, the structure presenting at least one mechanical reinforcing pillar received in said sacrificial layer, the method being characterized in that it comprises: a) making at least one well region (51, 52) in the sacrificial layer (2) by etching, at least in the entire thickness of the sacrificial layer (2), the well region defining at least one said mechanical pillar; b) depositing a first functionalization layer (4, 31) of a first material, relative to which the sacrificial layer is suitable for being etched selectively, the functionalization layer (4) filling at least one well region (51) at least partially and covering the free surface of the sacrificial layer (2) at least around the well region(s); and b′) depositing a filler layer (6, 32) of a second material different from the first material for terminating the filling of the well region(s) (5′), said filler layer (6) covering the first functionalization layer (4) at least in part around the well region(s) (5′), and planarizing the filler layer (6, 32), the pillar(s) being formed by the superposition of at least the first material and the second material in the well region(s); and releasing the electromechanical structure by removing at least partially the sacrificial layer (2). The invention also relates to an electromechanical structure obtained by the method.
摘要翻译：本发明涉及一种制造机电结构的方法，所述机电结构呈现第一衬底（1），所述第一衬底（1）包括覆盖在呈现自由表面的牺牲层（2）中的至少一层单晶材料层（1'），所述结构呈现至少一个所述方法的特征在于：其包括：a）至少在所述牺牲层的整个厚度中通过蚀刻在所述牺牲层（2）中制造至少一个阱区域（51,52）层（2），所述阱区限定至少一个所述机械支柱; b）沉积第一材料的第一官能化层（4,31），所述第一材料相对于所述第一材料，所述第一材料相对于所述第一材料，所述牺牲层适于被选择性地蚀刻，所述官能化层（4）至少部分填充至少一个阱区域（51）并且覆盖所述牺牲层（2）的至少围绕所述阱区域的自由表面; 和b'）沉积与所述第一材料不同的第二材料的填充层（6,32），以终止所述阱区域（5'）的填充，所述填充层（6）覆盖所述第一官能化层（ 4）至少部分地围绕所述阱区域（5'）周围，并且平坦化所述填充层（6,32），所述柱通过至少所述第一材料和所述第二材料的叠加形成井区; 以及通过至少部分去除所述牺牲层（2）来释放所述机电结构。本发明还涉及通过该方法获得的机电结构。

55. 发明申请

US20090170295A1 MANUFACTURING METHOD FOR A SEMI-CONDUCTOR ON INSULATOR SUBSTRATE COMPRISING A LOCALISED Ge ENRICHED STEP 有权
标题翻译：一种半导体制造方法，该绝缘体基板包含一个本地化的加固步骤
公开(公告)号：US20090170295A1
公开(公告)日：2009-07-02
申请号：US12340839
申请日：2008-12-22
申请人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
发明人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
IPC分类号： H01L21/20
CPC分类号： H01L21/32105 , H01L21/7624
摘要： The invention relates to a manufacturing method of a semi-conductor on insulator substrate from an SOI substrate comprising a surface layer of silicon on an electrically insulating layer, called buried insulating layer, wherein a layer of Si1-xGex is formed on the superficial layer of silicon.The method comprises the following steps: formation of a silicon oxide layer on the layer of Si1-xGex, formation of a silicon oxide layer on the layer of Si1-xGex, etching of the stack formed by the superficial layer of silicon, the layer of Si1-xGex and the silicon oxide layer, wherein the etching is carried out either up to the buried insulating layer to obtain an etched structure with at least one island of said stack, or up to the superficial layer of silicon to obtain an etched structure with at least one zone of silicon and at least one island of said stack, formation of a mask to protect against oxidation on the etched structure, wherein the protective mask only leaves visible the silicon oxide layer of the island, condensation of the germanium of the layer of Si1-xGex on the island to obtain an island comprising a layer that is enriched in germanium, or even a layer of germanium, on the buried insulating layer, with a silicon oxide layer on top of it.
摘要翻译：本发明涉及一种绝缘体上半导体衬底的制造方法，该SOI衬底包括在绝缘层上称为掩埋绝缘层的硅表面层，其中Si1-xGex层形成在表面层上硅。该方法包括以下步骤：在Si1-xGex层上形成氧化硅层，在Si1-xGex层上形成氧化硅层，蚀刻由硅表面层形成的叠层 Si1-xGex和氧化硅层，其中蚀刻直到埋入绝缘层进行，以获得具有至少一个所述堆叠的岛的蚀刻结构，或直到硅的表面层，以获得具有硅的至少一个区域和所述堆叠的至少一个岛，形成掩模以防止在蚀刻结构上的氧化，其中所述保护掩模仅使所述岛的氧化硅层可见，所述层的锗的冷凝的Si1-xGex，以在掩埋绝缘层上形成富含锗或甚至一层锗的层，其上面具有氧化硅层。

56. 发明申请

US20070105315A1 Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating C-MOS structures 有权
标题翻译：用于制造不同的第一和第二有源半导体区的方法及其用于制造C-MOS结构的方法
公开(公告)号：US20070105315A1
公开(公告)日：2007-05-10
申请号：US11584635
申请日：2006-10-23
申请人： Jean-Charles Barbe , Laurent Clavelier , Benoit Vianay , Yves Morand
发明人： Jean-Charles Barbe , Laurent Clavelier , Benoit Vianay , Yves Morand
IPC分类号： H01L21/336
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L21/823807 , H01L21/84 , H01L27/1203
摘要： A method according to the invention enables first and second active zones to be produced on a front face of a support, which said zones are respectively formed by first and second monocrystalline semi-conducting materials that are distinct from one another and preferably have identical crystalline structures. The front faces of the first and second active zones also present the advantage of being in the same plane. Such a method consists in particular in producing the second active zones by a crystallization step of the second semi-conducting material in monocrystalline form, from patterns made of second semi-conducting material in polycrystalline and/or amorphous form and from interface regions between said patterns and preselected first active zones. Moreover, the support is formed by stacking of a substrate and of an electrically insulating thin layer, the front face of the electrically insulating thin layer forming the front face of the support.
摘要翻译：根据本发明的方法使得能够在支撑体的前表面上产生第一和第二活性区域，所述区域分别由彼此不同的优选具有相同晶体结构的第一和第二单晶半导体材料形成。第一和第二活动区域的前表面也具有处于同一平面上的优点。这种方法特别在于通过第二半导体材料以单晶形式的结晶步骤从多晶和/或无定形形式的第二半导体材料制成的图案和由所述图案之间的界面区域产生第二活性区域和预选的第一活动区域。此外，通过堆叠基板和电绝缘薄层形成支撑体，电绝缘薄层的前表面形成支撑体的前表面。

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