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    • 52. 发明专利
    • Dimmer output emulation
    • GB2482946A
    • 2012-02-22
    • GB201112860
    • 2011-07-26
    • CIRRUS LOGIC INC
    • MELANSON JOHN L
    • H05B44/00
    • A dimmer output voltage emulator 408 causes a power converter interface circuit 402 to generate an emulated dimmer output voltage which emulates part of a cycle of an alternating current dimmer output. The emulated dimmer output voltage can decrease over time in multiple segments (fig 11) or with a concave parabolic waveform (fig 7, 708). The emulator can provide current (fig 6, IR) that interacts with components of the power interface circuit such as capacitor 412 and can comprise a pull-down circuit (fig 6, 602) to decrease the emulated voltage during a for a first period and a glue circuit (fig 6, 604) to hold the dimmer output voltage below a threshold for a second period. The first period can be from when a dimmer triac 106 ceases conduction during an AC supply voltage cycle until the supply voltage is below a threshold and the second period from then until the supply voltage begins to increase, when the triac fires. The emulated dimmer output voltage can correspond to an actual dimmer output voltage but is unaffected by a non-ideal dimmer output voltage, such as when a triac-based dimmer 102 prematurely shuts-down. By generating an emulated dimmer output voltage, the energy delivered to a load 310, such as a lamp, lighting system or light emitting diode (LED), corresponds to a dimming level setting.
    • 56. 发明专利
    • DE602006013989D1
    • 2010-06-10
    • DE602006013989
    • 2006-07-13
    • CIRRUS LOGIC INC
    • MELANSON JOHN L
    • H03M7/34
    • A digital signal processing system includes a delta sigma modulator that maintains a low pass output during quantizer overload prevention conditions. In at least one embodiment, the delta sigma modulator includes a quantizer overload protected delta sigma modulator with an N-order feedback-type loop filter. A quantizer of the delta sigma modulator provides feedback to at least the first two filter stages of the loop filter. The loop filter includes at least N successive filter stages and limits an output of an initial filter stage during quantizer overload prevention conditions. If limiting the output of the initial filter stage is insufficient to prevent quantizer overload, the delta sigma modulator can progressively limit an output of at least the next successive filter stage to prevent quantizer overload, where N is a positive integer greater than or equal to two (2).