专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20150054070A1 Electrostatic Discharge Protection Device and Manufacturing Method Thereof 审中-公开
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20150054070A1
公开(公告)日：2015-02-26
申请号：US13975024
申请日：2013-08-23
申请人： Tsung-Yi Huang , Wen-Yi Liao
发明人： Tsung-Yi Huang , Wen-Yi Liao
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66575 , H01L27/027 , H01L29/1045
摘要： The present invention discloses an electrostatic discharge (ESD) protection device and a manufacturing method thereof. The ESD protection device includes: a P-type well, a gate structure, an N-type source, an N-type drain, and a P-type lightly doped drain. The P-type lightly doped drain is formed in the P-type well, and at least part of the P-type lightly doped drain is beneath a spacer of the gate structure to reduce a trigger voltage of the electrostatic discharge protection device.
摘要翻译：本发明公开了一种静电放电（ESD）保护装置及其制造方法。 ESD保护器件包括：P型阱，栅极结构，N型源极，N型漏极和P型轻掺杂漏极。在P型阱中形成P型轻掺杂漏极，并且至少部分P型轻掺杂漏极位于栅极结构的间隔物的下方，以降低静电放电保护器件的触发电压。

52. 发明授权

US08860082B2 Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof 有权
标题翻译：瞬态电压抑制电路及其二极管装置及其制造方法
公开(公告)号：US08860082B2
公开(公告)日：2014-10-14
申请号：US13549501
申请日：2012-07-15
申请人： Tsung-Yi Huang , Jin-Lian Su
发明人： Tsung-Yi Huang , Jin-Lian Su
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/66136 , H01L21/265 , H01L21/76224 , H01L27/0255 , H01L27/0814 , H01L29/0649
摘要： The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.
摘要翻译：本发明公开了一种瞬态电压抑制器（TVS）电路及其二极管装置及其制造方法。 TVS电路用于耦合到受保护电路以限制输入到保护电路的瞬态电压的幅度。 TVS电路包括抑制器装置和至少二极管装置。二极管器件形成在衬底中，其包括：在衬底中形成的阱; 形成在所述上表面下方的分离区域; 阳极区域和阴极区域，其分别形成在上表面下方的分离区域的两侧，其中阳极区域和阴极区域被分离区域分离; 以及掩埋层，其形成在阱下方的衬底中，具有较高的杂质密度和与该阱相同的导电类型。

53. 发明授权

US08859373B2 High voltage device and manufacturing method thereof 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US08859373B2
公开(公告)日：2014-10-14
申请号：US14056613
申请日：2013-10-17
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78 , H01L29/10
CPC分类号： H01L29/66681 , H01L29/0623 , H01L29/1083 , H01L29/66659 , H01L29/7813 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the substrate. The source and drain are located at both sides of the gate below the upper surface respectively, and the source and drain are separated by the gate. The drift region is located at least between the gate and the drain. The mitigation region is formed below the drift region, and the drift region has an edge closer to the source. A vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在衬底中。高电压装置包括：栅极，源极和漏极，漂移区和缓解区。栅极形成在衬底的上表面上。源极和漏极分别位于栅极下方的两侧，源极和漏极由栅极分开。漂移区域至少位于栅极和漏极之间。缓冲区形成在漂移区下方，漂移区具有靠近源的边。漂移区域的这个边缘与缓解区域之间的垂直距离小于或等于漂移区域的深度的五倍。

54. 发明授权

US08841723B2 LDMOS device having increased punch-through voltage and method for making same 有权
标题翻译：具有增加穿通电压的LDMOS器件及其制造方法
公开(公告)号：US08841723B2
公开(公告)日：2014-09-23
申请号：US12720834
申请日：2010-03-10
申请人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hung-Der Su
发明人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hung-Der Su
IPC分类号： H01L29/66 , H01L29/08 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/66681
摘要： The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage.
摘要翻译：本发明公开了一种具有增加的穿通电压的LDMOS器件及其制造方法。 LDMOS器件包括：衬底; 在基板中形成的第一导电类型的阱; 形成在衬底中的隔离区; 井中的第二导电类型的体区; 身体的一个来源; 井中排水基板上的栅极结构; 以及在身体区域下面的第一导电型掺杂区域，用于增加穿通电压。

55. 发明申请

US20140159048A1 High Electron Mobility Transistor and Manufacturing Method Thereof 有权
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US20140159048A1
公开(公告)日：2014-06-12
申请号：US13898374
申请日：2013-05-20
申请人： Chih-Fang Huang , Po-Chin Peng , Tsung-Chieh Hsiao , Ya-Hsien Liu , K.C. Chang , Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang , Tsung-Yu Yang , Ting-Fu Chang
发明人： Chih-Fang Huang , Po-Chin Peng , Tsung-Chieh Hsiao , Ya-Hsien Liu , K.C. Chang , Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang , Tsung-Yu Yang , Ting-Fu Chang
IPC分类号： H01L29/778
CPC分类号： H01L29/66462 , H01L29/0657 , H01L29/2003 , H01L29/66431 , H01L29/7789
摘要： The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.
摘要翻译：本发明公开了一种高电子迁移率晶体管（HEMT）及其制造方法。 HEMT器件包括：衬底，第一氮化镓（GaN）层; P型GaN层，第二GaN层，势垒层，栅极，源极和漏极。第一GaN层形成在基板上，并且具有从横截面视图的阶梯状轮廓。 P型GaN层形成在阶梯状轮廓的上台阶面上，具有垂直侧壁。第二GaN层形成在P型GaN层上。阻挡层形成在第二GaN层上。在阻挡层与第一和第二GaN层之间的接合处形成二维电子气体区域。门形成在垂直侧壁的外侧。

56. 发明申请

US20140151796A1 HYBRID HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：混合高压器件及其制造方法
公开(公告)号：US20140151796A1
公开(公告)日：2014-06-05
申请号：US14176973
申请日：2014-02-10
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/7817 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/402 , H01L29/42368 , H01L29/4238 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
摘要翻译：本发明公开了一种混合式高压装置及其制造方法。混合高压器件形成在第一导电型衬底中，并且包括至少一个横向双扩散金属氧化物半导体（LDMOS）器件区域和至少一个通气器件区域，其中LDMOS器件区域和通气器件区域被连接在宽度方向上以交替的顺序布置。此外，LDMOS器件区域和通风装置区域的相应的高压井，源极，漏极，体区和栅极分别彼此连接。

57. 发明申请

US20140117443A1 DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20140117443A1
公开(公告)日：2014-05-01
申请号：US14146512
申请日：2014-01-02
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L29/423 , H01L29/66 , H01L21/28 , H01L29/78
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

58. 发明申请

US20140061658A1 High Electron Mobility Transistor and Manufacturing Method Thereof 审中-公开
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US20140061658A1
公开(公告)日：2014-03-06
申请号：US13603392
申请日：2012-09-04
申请人： Chien-Wei Chiu , Tsung-Yi Huang
发明人： Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L29/778 , H01L21/338
CPC分类号： H01L29/1033 , H01L21/76224 , H01L29/1029 , H01L29/2003 , H01L29/42364 , H01L29/66462 , H01L29/7787
摘要： The present invention discloses an enhanced mode high electron mobility transistor (HEMT) which includes: a P-type gallium nitride (GaN) layer; a barrier layer, which is formed on and connected to the GaN layer; a dielectric layer, which is formed on and connected to the GaN layer, wherein the barrier layer does not overlap at least part of the dielectric layer; a gate, which is formed on the dielectric layer for receiving a gate voltage; and a source and a drain, which are formed at two sides of the gate on the GaN layer respectively; wherein a two dimensional electron gas (2DEG) is formed at a junction of the GaN layer and the barrier layer which does not include a portion of the junction below the gate, and the 2DEG does not electrically connect the source to the drain when there is no voltage applied to the gate.
摘要翻译：本发明公开了一种增强型高电子迁移率晶体管（HEMT），其包括：P型氮化镓（GaN）层; 阻挡层，其形成在GaN层上并连接到GaN层; 形成在GaN层上并连接到GaN层的电介质层，其中阻挡层不与电介质层的至少一部分重叠; 栅极，其形成在用于接收栅极电压的电介质层上; 以及源极和漏极，其分别形成在GaN层上的栅极的两侧; 其中在GaN层和阻挡层的结合处形成二维电子气（2DEG），其不包括在栅极下方的结的一部分，并且当存在时，2DEG不将源电连接到漏极没有电压施加到门。

59. 发明申请

US20140045313A1 HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：高压器件及其制造方法
公开(公告)号：US20140045313A1
公开(公告)日：2014-02-13
申请号：US14055622
申请日：2013-10-16
申请人： Tsung-Yi Huang , Kuo-Hsuan Lo
发明人： Tsung-Yi Huang , Kuo-Hsuan Lo
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/42368 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; agate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件包括：第一导电型衬底，其中形成隔离区以限定器件区域; 形成在第一导电类型衬底上的玛瑙; 在器件区域中分别形成并位于栅极两侧的源极和漏极，并掺杂有第二导电类型杂质; 第二导电型阱，其形成在第一导电类型基板中，并且从俯视图围绕漏极; 以及第一深沟槽隔离结构，其形成在第一导电类型基板中，并且从顶视图位于源极和漏极之间的第二导电类型阱中，其中第一深沟槽隔离结构的深度比第二导电类型井从横截面图。

60. 发明申请

US20140001551A1 Lateral Double Diffused Metal Oxide Semiconductor Device and Manufacturing Method Thereof 审中-公开
标题翻译：横向双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20140001551A1
公开(公告)日：2014-01-02
申请号：US13538234
申请日：2012-06-29
申请人： Tsung-Yi Huang
发明人： Tsung-Yi Huang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0692 , H01L29/0878 , H01L29/0882 , H01L29/1083 , H01L29/42368 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device is formed in a first conductive type substrate, and includes a high voltage well, a first field oxide region, at least one second field oxide region, a source, a drain, a body region, and a gate. The second field oxide region is located between the first field oxide region and the drain from top view. The distribution of the concentration of the second conductive type impurities in the high voltage well is related to the location of the second field oxide region.
摘要翻译：本发明公开了一种横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 LDMOS器件形成在第一导电型衬底中，并且包括高电压阱，第一场氧化物区域，至少一个第二场氧化物区域，源极，漏极，体区域和栅极。第二场氧化物区域从顶视图位于第一场氧化物区域和漏极之间。第二导电型杂质在高压井中的浓度分布与第二场氧化物区域的位置有关。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式