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51. 发明授权

US08228102B1 Phase-locked loop architecture and clock distribution system 有权
标题翻译：锁相环架构和时钟分配系统
公开(公告)号：US08228102B1
公开(公告)日：2012-07-24
申请号：US12717062
申请日：2010-03-03
申请人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
发明人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
IPC分类号： H03L7/06
CPC分类号： H03L7/23 , G06F1/10 , H03L7/0807 , H03L7/183 , H03L7/197 , H03L7/1974 , H04L7/0331
摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条侧。可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。每个PMA三元组模块包括第一，第二和第三通道。第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。还公开了其它实施例和特征。

52. 发明授权

US08126079B1 High-speed serial data signal interface circuitry with multi-data-rate switching capability 有权
标题翻译：具有多数据速率切换功能的高速串行数据信号接口电路
公开(公告)号：US08126079B1
公开(公告)日：2012-02-28
申请号：US11824862
申请日：2007-07-03
申请人： Thungoc M. Tran , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Wilson Wong , Allen Chan
发明人： Thungoc M. Tran , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Wilson Wong , Allen Chan
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H03L7/22 , H04L7/0008
摘要： High-speed serial data signal transmitter and/or receiver circuitry is able to dynamically switch between handling data at two (or more) different data rates. Such a switch can be made very rapidly and with no requirement for reprogramming or reconfiguring the circuitry. Circuitry for glitchlessly switching between clock signals having different frequencies is also provided and may be used in the above-mentioned transmitter and/or receiver circuitry.
摘要翻译：高速串行数据信号发射机和/或接收机电路能够以两种（或多种）不同的数据速率在处理数据之间动态切换。这样的开关可以非常快速地进行，并且不需要重新编程或重新配置电路。还提供了用于在具有不同频率的时钟信号之间无差错地切换的电路，并且可以在上述发射机和/或接收机电路中使用。

53. 发明授权

US07899649B1 Signal detect for high-speed serial interface 有权
标题翻译：信号检测用于高速串行接口
公开(公告)号：US07899649B1
公开(公告)日：2011-03-01
申请号：US12053884
申请日：2008-03-24
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
IPC分类号： G06F19/00
CPC分类号： H03K5/19 , H03K19/1774 , H03K19/17744 , H03K19/1778
摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
摘要翻译：串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

54. 发明授权

US07791370B1 Clock distribution techniques for channels 有权
标题翻译：频道的时钟分配技术
公开(公告)号：US07791370B1
公开(公告)日：2010-09-07
申请号：US12470455
申请日：2009-05-21
申请人： Tim Tri Hoang , Thungoc M. Tran , Wilson Wong , Sergey Shumarayev
发明人： Tim Tri Hoang , Thungoc M. Tran , Wilson Wong , Sergey Shumarayev
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F1/10
摘要： A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.
摘要翻译：电路包括第一区域，第二区域和第三区域。第二区域包括产生时钟信号的锁定环路电路。锁定环电路接收与第一区域中产生的噪声隔离的电源电压。第三区域包括多个通道的四通道，并且时钟线耦合以将在第二区域中产生的至少一个时钟信号路由到每个四通道中的通道。第三个区域与电路中的第二个区域分开。

55. 发明申请

US20080258765A1 Low-power transceiver architectures for programmable logic integrated circuit devices 有权
标题翻译：用于可编程逻辑集成电路器件的低功耗收发器架构
公开(公告)号：US20080258765A1
公开(公告)日：2008-10-23
申请号：US12214466
申请日：2008-06-18
申请人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
发明人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Richard G. Cliff
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17744 , H03K19/17784
摘要： High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.
摘要翻译：可编程逻辑器件集成电路（“PLD”）上的高速串行接口或收发器电路包括允许PLD满足广泛可能的用户需求或应用的功能。该范围包括高性能应用和PLD降低功耗很重要的应用。在后一种情况下，可以使用各种特征中的任何一种或多种来帮助降低功耗。

56. 发明授权

US07414429B1 Integration of high-speed serial interface circuitry into programmable logic device architectures 有权
标题翻译：将高速串行接口电路集成到可编程逻辑器件架构中
公开(公告)号：US07414429B1
公开(公告)日：2008-08-19
申请号：US11486867
申请日：2006-07-14
申请人： In Whan Kim , Sergey Shumarayev , Tim Tri Hoang , Wilson Wong , Thungoc M. Tran
发明人： In Whan Kim , Sergey Shumarayev , Tim Tri Hoang , Wilson Wong , Thungoc M. Tran
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/0175 , H01L25/00
CPC分类号： H03K19/17744
摘要： The architecture of a programmable logic device (“PLD”) is modified in one or more of several respects to facilitate inclusion of high-speed serial interface (“HSSI”) circuitry in the PLD. For example, the HSSI circuitry is preferably located along one side of the device, taking the place of regular peripheral IO circuitry in that area. Certain portions of the core logic circuitry are modified to better interface with the HSSI circuitry.
摘要翻译：可编程逻辑器件（“PLD”）的架构在几个方面中的一个或多个方面进行了修改，以便于在PLD中包含高速串行接口（“HSSI”）电路。例如，HSSI电路优选地位于设备的一侧，代替该区域中的常规外设IO电路。核心逻辑电路的某些部分被修改以更好地与HSSI电路接口。

57. 发明授权

US07245240B1 Integrated circuit serializers with two-phase global master clocks 有权
标题翻译：具有两相全球主时钟的集成电路串行器
公开(公告)号：US07245240B1
公开(公告)日：2007-07-17
申请号：US11370727
申请日：2006-03-07
申请人： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev
发明人： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H03K5/15013
摘要： Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.
摘要翻译：提供集成电路串行化器电路，其将并行数据转换为集成电路上的串行数据。两相全局串行器主时钟发生器使用四相内部时钟来生成两相全局串行器主时钟。两相全局串行器主时钟使用分布路径全局分布在集成电路上。集成电路具有多个串行通信通道，每个通道具有相关联的串行器。每个串行器包含从全局串行器主时钟的两个相位导出多个时钟信号的电路。每个串行器使用派生时钟将并行数据转换为串行数据，以便通过其相关联的串行通信通道进行传输。串行器每个都包含两个较小的串行器，它们将第一和第二组并行数据转换为第一和第二串行输出。每个串行器中的2：1串行器合并第一个和第二个串行输出。

58. 发明授权

US08811555B2 Clock and data recovery circuitry with auto-speed negotiation and other possible features 有权
标题翻译：时钟和数据恢复电路，具有自动速度协商和其他可能的功能
公开(公告)号：US08811555B2
公开(公告)日：2014-08-19
申请号：US12700433
申请日：2010-02-04
申请人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
发明人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
IPC分类号： H04L7/00 , H03L7/081 , H04L7/033 , H03L7/08
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/183 , H04L7/0337
摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).
摘要翻译：集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。

59. 发明授权

US08744012B1 On-chip eye viewer architecture for highspeed transceivers 有权
标题翻译：用于高速收发器的片上眼睛查看器架构
公开(公告)号：US08744012B1
公开(公告)日：2014-06-03
申请号：US13369108
申请日：2012-02-08
申请人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
发明人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
IPC分类号： H03K9/00
CPC分类号： H04L1/203 , G01R31/31711
摘要： System, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with a serial input signal either during or after equalization. The device may include an equalizer and eye viewer circuitry configured to select a node of the equalizer for eye monitoring of the input signal, which may be during or after equalization. In one embodiment, the eye viewer circuitry may provide a separate sampler for each respective node, while sharing a control logic and phase interpolator among the samplers. The eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the serial input signal, as seen from the selected node of the equalizer.
摘要翻译：提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和设备。例如，集成电路器件的一个实施例可能能够在均衡期间或之后确定与串行输入信号相关联的眼图。该装置可以包括均衡器和眼睛观察器电路，其被配置为选择均衡器的节点，用于在均衡期间或之后的输入信号的眼睛监视。在一个实施例中，眼睛观察器电路可以为每个相应节点提供单独的采样器，同时在采样器之间共享控制逻辑和相位插值器。从均衡器的选定节点看，眼睛观察器电路可以确定与串行输入信号相关联的眼图的水平和垂直边界。

60. 发明授权

US08542042B1 Phase-locked loop architecture and clock distribution system 有权
标题翻译：锁相环架构和时钟分配系统
公开(公告)号：US08542042B1
公开(公告)日：2013-09-24
申请号：US13532528
申请日：2012-06-25
申请人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff
发明人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff
IPC分类号： H03L7/06
CPC分类号： H03L7/23 , G06F1/10 , H03L7/0807 , H03L7/183 , H03L7/197 , H03L7/1974 , H04L7/0331
摘要： One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种可断裂的PLL电路。断裂PLL电路包括产生第一频率输出的第一锁相环电路，第二锁相环电路; 布置成产生第二频率输出和多个共享输出资源。可重构电路被布置成使得第一和第二频率输出中的任一个可由多个共享输出资源中的每一个接收。另一实施例涉及一种集成电路，其包括多个PMA模块，多个多用途PLL电路和可编程时钟网络。可编程时钟网络被布置为允许由多用途PLL电路输出的时钟信号被PMA模块选择性地用于收发器应用或由用于非收发器应用的其它电路。还公开了其它实施例和特征。

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