专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20070102770A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20070102770A1
公开(公告)日：2007-05-10
申请号：US11619451
申请日：2007-01-03
申请人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
发明人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
IPC分类号： H01L29/76
CPC分类号： H01L27/1288 , G02F2001/136236 , H01L21/31144 , H01L21/32139 , H01L27/1214 , H01L27/124 , H01L29/41733
摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

52. 发明申请

US20060091396A1 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060091396A1
公开(公告)日：2006-05-04
申请号：US11249500
申请日：2005-10-14
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L29/04
CPC分类号： H01L27/3279 , H01L27/124 , H01L27/1288 , H01L51/0023 , H01L51/56
摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.
摘要翻译：本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

53. 发明申请

US20060076562A1 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060076562A1
公开(公告)日：2006-04-13
申请号：US11215067
申请日：2005-08-29
申请人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
发明人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
IPC分类号： H01L29/04 , H01L27/148
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/12 , H01L29/458
摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode at on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
摘要翻译：本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地与扩散阻挡层接触并且与栅电极上的源电极相对; 以及电连接到漏电极的像素电极。

54. 发明申请

US20050221546A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050221546A1
公开(公告)日：2005-10-06
申请号：US11082967
申请日：2005-03-18
申请人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
发明人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
IPC分类号： G02F1/1368 , G09F9/30 , G09G3/36 , G09G3/38 , H01L21/00 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L27/1288 , G02F2001/136236 , H01L21/31144 , H01L21/32139 , H01L27/1214 , H01L27/124 , H01L29/41733
摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

55. 发明授权

US08952376B2 Thin film transistor, and method of manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US08952376B2
公开(公告)日：2015-02-10
申请号：US13049547
申请日：2011-03-16
申请人： Je-Hun Lee , Joo-Han Kim
发明人： Je-Hun Lee , Joo-Han Kim
IPC分类号： H01L29/10 , H01L29/12 , H01L31/00 , H01L29/786 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/78648 , H01L29/78696
摘要： A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a first gate electrode and an active layer including a crystalline oxide semiconductor which is insulated from the first gate electrode by a first insulating layer and the active layer is arranged to overlap the first gate electrode. A source electrode is formed including at least a portion overlaps the active layer, and a drain electrode is arranged being spaced apart from the source electrode and at least a portion of the drain electrode overlaps the active layer, wherein the source electrode and the drain electrode are insulated from the first gate electrode by the first insulating layer.
摘要翻译：提供薄膜晶体管及其制造方法。薄膜晶体管包括第一栅电极和有源层，其包括通过第一绝缘层与第一栅电极绝缘的结晶氧化物半导体，并且有源层布置成与第一栅电极重叠。源极电极形成为包括至少一部分与有源层重叠的部分，并且排列电极被布置成与源电极间隔开，并且漏电极的至少一部分与有源层重叠，其中源电极和漏电极通过第一绝缘层与第一栅极绝缘。

56. 发明授权

US08455277B2 Thin film transistor array panel and manufacturing method thereof 失效
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08455277B2
公开(公告)日：2013-06-04
申请号：US13523767
申请日：2012-06-14
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a plurality of gate lines, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括多个栅极线，多个公共电极，覆盖栅极线和公共电极的栅极绝缘层，形成在栅极绝缘层上的多个半导体层，多个包括多个源电极并形成在半导体层上的数据线，形成在半导体层上的多个漏电极以及与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生不透明金属Sn或Zn。

57. 发明授权

US08372701B2 Thin film transistor array panel including layered line structure and method for manufacturing the same 有权
公开(公告)号：US08372701B2
公开(公告)日：2013-02-12
申请号：US12576217
申请日：2009-10-08
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L21/00
CPC分类号： H01L27/1214 , H01L27/1225 , H01L27/124
摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

58. 发明授权

US08288771B2 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US08288771B2
公开(公告)日：2012-10-16
申请号：US13204553
申请日：2011-08-05
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L29/786 , H01L21/336 , H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

59. 发明授权

US08252639B2 Thin film transistor array panel and method for manufacturing the same 失效
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08252639B2
公开(公告)日：2012-08-28
申请号：US12951981
申请日：2010-11-22
申请人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
发明人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
IPC分类号： H01L21/00
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/12 , H01L29/458
摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
摘要翻译：本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在所述栅极绝缘层上且与所述栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

60. 发明授权

US08035102B2 Display substrate, method of manufacturing the same and display panel having the same 有权
标题翻译：显示基板，其制造方法以及具有该基板的显示面板
公开(公告)号：US08035102B2
公开(公告)日：2011-10-11
申请号：US11646832
申请日：2006-12-27
申请人： Je-Hun Lee , Young-Min Kim , Bo-Sung Kim , Jun-Young Lee , Sung-Wook Kang
发明人： Je-Hun Lee , Young-Min Kim , Bo-Sung Kim , Jun-Young Lee , Sung-Wook Kang
IPC分类号： H01L29/04
CPC分类号： H01L51/102 , G02F1/13439 , H01L27/283 , H01L51/0541 , H01L51/0545
摘要： An improved display substrate is provided to reduce surface defects on insulating layers of organic thin film transistors. Related methods of manufacture are also provided. In one example, a display substrate includes a base, a plurality of data lines, a plurality of gate lines, a pixel defined by the data lines and the gate lines, an organic thin film transistor, and a pixel electrode. The data lines are on the base and are oriented in a first direction. The gate lines are oriented in a second direction that crosses the first direction. The organic thin film transistor includes a source electrode electrically connected to one of the data lines, a gate electrode electrically connected to one of the gate lines, and an organic semiconductor layer. The pixel electrode is disposed in the pixel and electrically connected to the organic thin film transistor. The pixel electrode comprises a transparent oxynitride.
摘要翻译：提供改进的显示基板以减少有机薄膜晶体管的绝缘层上的表面缺陷。还提供了相关的制造方法。在一个示例中，显示基板包括基底，多条数据线，多条栅极线，由数据线和栅极线限定的像素，有机薄膜晶体管和像素电极。数据线在基座上并且朝向第一方向。栅极线在与第一方向交叉的第二方向上取向。有机薄膜晶体管包括电连接到数据线之一的源电极，电连接到栅极线之一的栅电极和有机半导体层。像素电极设置在像素中并电连接到有机薄膜晶体管。像素电极包括透明氧氮化物。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式