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51. 发明授权

US08259787B2 High-speed decoder for a multi-pair gigabit transceiver 有权
标题翻译：用于多对千兆位收发器的高速解码器
公开(公告)号：US08259787B2
公开(公告)日：2012-09-04
申请号：US12633451
申请日：2009-12-08
申请人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
发明人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
IPC分类号： H03H7/30
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H03M13/256 , H03M13/41 , H03M13/6331 , H04B3/23 , H04B3/32 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0059 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is generated. Each of the pre-computed values is combined with the tail value to generate a tentative sample. One of the tentative samples is selected as the input signal to the decoder. In one aspect of the system, tentative samples are saturated and then stored in a set of registers before being outputted to a multiplexer which selects one of the tentative samples as the input signal to the decoder. This operation of storing the tentative samples in the registers before providing the tentative samples to the multiplexer facilitates high-speed operation by breaking up a critical path of computations into substantially balanced first and second portions, the first portion including computations in the decision-feedback equalizer and the multiple decision feedback equalizer, the second portion including computations in the decoder.
摘要翻译：一种用于基于从判决反馈均衡器接收的尾值和系数值的子集，将来自多决策反馈均衡器的输入信号提供给解码器的方法和系统。产生一组基于系数值子集的预计算值。每个预先计算的值与尾值组合以生成临时样本。选择一个暂定样本作为解码器的输入信号。在系统的一个方面，暂定样本被饱和，然后被存储在一组寄存器中，然后被输出到多路复用器，该多路复用器选择一个暂定采样作为解码器的输入信号。在将暂定样本提供给多路复用器之前将暂定样本存储在寄存器中的这种操作便于通过将计算的关键路径分解为基本上平衡的第一和第二部分进行高速操作，第一部分包括判决反馈均衡器和多个判决反馈均衡器，第二部分包括解码器中的计算。

52. 发明授权

US07936840B2 Demodulator for a multi-pair gigabit transceiver 有权
标题翻译：用于多对千兆位收发器的解调器
公开(公告)号：US07936840B2
公开(公告)日：2011-05-03
申请号：US12698639
申请日：2010-02-02
申请人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
发明人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
IPC分类号： H04B15/00
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and a decoder. The feedforward equalizer comprises a non-adaptive filter and a gain stage. The non-adaptive filter receives the signal samples and produces a filtered signal. The gain stage adjusts the gain of the feedforward equalizer by adjusting the amplitude of the filtered signal. The amplitude of the filtered signal is adjusted so that it fits in the operational range of the decoder. The feedforward equalizer does not affect the sampling phase setting of the timing recovery module of the receiver.
摘要翻译：前馈均衡器，用于均衡来自远程发射机的接收机接收的信号样本序列。前馈均衡器具有增益并且被包括在接收机中，该接收机包括用于设置采样相位和解码器的定时恢复模块。前馈均衡器包括非自适应滤波器和增益级。非自适应滤波器接收信号样本并产生滤波信号。增益级通过调整滤波信号的幅度来调节前馈均衡器的增益。调整滤波后的信号的幅度使其适合于解码器的操作范围。前馈均衡器不影响接收机的定时恢复模块的采样相位设置。

53. 发明授权

US07656938B2 Demodulator for a multi-pair gigabit transceiver 有权
标题翻译：用于多对千兆位收发器的解调器
公开(公告)号：US07656938B2
公开(公告)日：2010-02-02
申请号：US10772079
申请日：2004-02-03
申请人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
发明人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
IPC分类号： H03K5/159
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0047 , H04L1/0054 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/03885 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and a decoder. The feedforward equalizer comprises a non-adaptive filter and a gain stage. The non-adaptive filter receives the signal samples and produces a filtered signal. The gain stage adjusts the gain of the feedforward equalizer by adjusting the amplitude of the filtered signal. The amplitude of the filtered signal is adjusted so that it fits in the operational range of the decoder. The feedforward equalizer does not affect the sampling phase setting of the timing recovery module of the receiver.
摘要翻译：前馈均衡器，用于均衡来自远程发射机的接收机接收的信号样本序列。前馈均衡器具有增益并且被包括在接收机中，该接收机包括用于设置采样相位和解码器的定时恢复模块。前馈均衡器包括非自适应滤波器和增益级。非自适应滤波器接收信号样本并产生滤波信号。增益级通过调整滤波信号的幅度来调节前馈均衡器的增益。调整滤波后的信号的幅度使其适合于解码器的操作范围。前馈均衡器不影响接收机的定时恢复模块的采样相位设置。

54. 发明授权

US07562098B2 Opportunistic directory cache 有权
标题翻译：机会目录缓存
公开(公告)号：US07562098B2
公开(公告)日：2009-07-14
申请号：US11204626
申请日：2005-08-16
申请人： Venkataraman Ramanathan , Ramanathan Ganapathy , Yun Lin , David Kruse
发明人： Venkataraman Ramanathan , Ramanathan Ganapathy , Yun Lin , David Kruse
IPC分类号： G06F17/30
CPC分类号： H04L67/2814 , G06F17/30902 , H04L67/2828 , H04L67/2852 , H04L69/329 , Y10S707/99942 , Y10S707/99945 , Y10S707/99948
摘要： An opportunistic directory cache and method of usage reduce the number of calls between a client and server for file information, reducing the wastage of network resources and server resources. The expirable directory cache can be refreshed any time an appropriate directory enumeration call is made to the server, and is capable of being partially rather than completely invalidated in response to an indication that the file information of a file listed in the cache has or will change. If the affected file is identifiable, the entry in the cache for that file is invalidated, i.e. it is no longer useful for serving file information. If the affected file is not identifiable, then a first character projection of the file name is invalidated in the cache. In this manner, the directory cache is maintained with minimum resources and is persisted to the greatest extent possible, increasing its likelihood of usefulness.
摘要翻译：机会性目录缓存和使用方法可减少客户端与服务器之间的文件信息调用次数，减少网络资源和服务器资源的浪费。可以随时对服务器进行适当的目录枚举调用来刷新可终止的目录高速缓存，并且能够响应于缓存中列出的文件信息或将要改变的指示而部分地而不是完全无效。如果受影响的文件是可识别的，则该文件的高速缓存中的条目无效，即对于提供文件信息不再有用。如果受影响的文件不可识别，则文件名的第一个字符投影将在缓存中无效。以这种方式，以最小的资源维护目录缓存并且最大程度地持续存在目录缓存，从而增加其可用性。

55. 发明申请

US20090067559A1 SYSTEM AND METHOD FOR HIGH-SPEED DECODING AND ISI COMPENSATION IN A MULTI-PAIR TRANSCEIVER SYSTEM 失效
标题翻译：多对数收发系统中高速解码和ISI补偿的系统和方法
公开(公告)号：US20090067559A1
公开(公告)日：2009-03-12
申请号：US12269697
申请日：2008-11-12
申请人： Oscar E. Azazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
发明人： Oscar E. Azazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
IPC分类号： H04B1/10 , H03D1/06
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H03M13/256 , H03M13/41 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/0059 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03203 , H04L25/03267 , H04L25/03324 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03458 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03643 , H04L2025/03745
摘要： A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.
摘要翻译：一种用于以分叉方式向输入信号提供ISI补偿的方法和系统。 ISI补偿分两阶段提供，第一级补偿由发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由多对传输信道的特性引起的ISI分量。在系统启动期间，在具有特性反馈增益因子K的逆响应滤波器中执行第一级ISI补偿。第二级ISI补偿由单个DFE与由维特比解码器输出的暂定决定操作的MDFE组合执行。当第二级的DFE达到收敛时，第一级的反馈增益因子K变为零。

56. 发明申请

US20090044070A1 SYSTEM AND METHOD FOR TRELLIS DECODING IN A MULTI-PAIR TRANSCEIVER SYSTEM 有权
标题翻译：用于多对收发器系统中的TRELLIS解码的系统和方法
公开(公告)号：US20090044070A1
公开(公告)日：2009-02-12
申请号：US12247064
申请日：2008-10-07
申请人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
发明人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/0059 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.
摘要翻译：一种用于对根据多状态编码方案编码并通过计算从码字的接收字的距离而在多维传输信道上传送的信息信号的方法和系统。一维（1D）输入信号在一对符号解码器中被处理，被实现为查找表，以产生一对1D误差，其中每一个代表在两个不相交中的一个中的输入信号和符号之间的距离度量符号子集。基于多状态编码方案组合1D误差，以产生一组多维误差项。多维误差项中的每一个对应于接收到的字和最近的码字之间的距离。

57. 发明申请

US20080049826A1 Graphics Accelerator 失效
标题翻译：图形加速器
公开(公告)号：US20080049826A1
公开(公告)日：2008-02-28
申请号：US11846195
申请日：2007-08-28
申请人： Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H04L27/01 , H04B1/10
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

58. 发明申请

US20060245487A1 High-speed decoder for a multi-pair gigabit transceiver 有权
公开(公告)号：US20060245487A1
公开(公告)日：2006-11-02
申请号：US11257810
申请日：2005-10-25
申请人： Oscar Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
发明人： Oscar Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
IPC分类号： H03H7/30
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H03M13/256 , H03M13/41 , H03M13/6331 , H04B3/23 , H04B3/32 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0059 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is generated. Each of the pre-computed values is combined with the tail value to generate a tentative sample. One of the tentative samples is selected as the input signal to the decoder. In one aspect of the system, tentative samples are saturated and then stored in a set of registers before being outputted to a multiplexer which selects one of the tentative samples as the input signal to the decoder. This operation of storing the tentative samples in the registers before providing the tentative samples to the multiplexer facilitates high-speed operation by breaking up a critical path of computations into substantially balanced first and second portions, the first portion including computations in the decision-feedback equalizer and the multiple decision feedback equalizer, the second portion including computations in the decoder.

59. 发明申请

US20060238256A1 Gigabit ethernet transceiver with analog front end 有权
公开(公告)号：US20060238256A1
公开(公告)日：2006-10-26
申请号：US11417073
申请日：2006-05-02
申请人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03G3/00
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

60. 发明申请

US20060041633A1 Opportunistic directory cache 有权
公开(公告)号：US20060041633A1
公开(公告)日：2006-02-23
申请号：US11204626
申请日：2005-08-16
申请人： Venkataraman Ramanathan , Ramanathan Ganapathy , Yun Lin , David Kruse
发明人： Venkataraman Ramanathan , Ramanathan Ganapathy , Yun Lin , David Kruse
IPC分类号： G06F15/16 , G06F12/00
CPC分类号： H04L67/2814 , G06F17/30902 , H04L67/2828 , H04L67/2852 , H04L69/329 , Y10S707/99942 , Y10S707/99945 , Y10S707/99948
摘要： An opportunistic directory cache and method of usage reduce the number of calls between a client and server for file information, reducing the wastage of network resources and server resources. The expirable directory cache can be refreshed any time an appropriate directory enumeration call is made to the server, and is capable of being partially rather than completely invalidated in response to an indication that the file information of a file listed in the cache has or will change. If the affected file is identifiable, the entry in the cache for that file is invalidated, i.e. it is no longer useful for serving file information. If the affected file is not identifiable, then a first character projection of the file name is invalidated in the cache. In this manner, the directory cache is maintained with minimum resources and is persisted to the greatest extent possible, increasing its likelihood of usefulness.

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