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51. 发明申请

US20050237847A1 Semiconductor device with source line and fabrication method thereof 审中-公开
公开(公告)号：US20050237847A1
公开(公告)日：2005-10-27
申请号：US11171300
申请日：2005-07-01
申请人： Akira Goda , Mitsuhiro Noguchi
发明人： Akira Goda , Mitsuhiro Noguchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C8/00
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor device comprises a plurality of field-effect transistors and a common source line. Each of the plurality of memory cell transistors includes a semiconductor region of a first conductivity type formed in a semiconductor substrate, a source region and a drain region of a second conductivity type formed in the semiconductor region, an information storage portion capable of electrically writing and erasing data, and at least one control gate electrode including a conductive layer. The common source line is formed on the semiconductor region of the first conductivity type, and electrically connects the source regions of the memory cell transistors. The common source line includes a conductive layer that has a film thickness substantially equal to a film thickness of the conductive layer included in the control gate electrode and is formed of the same material as that of the conductive layer included in the control gate electrode.

52. 发明授权

US06917072B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06917072B2
公开(公告)日：2005-07-12
申请号：US10393946
申请日：2003-03-24
申请人： Mitsuhiro Noguchi , Akira Goda
发明人： Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L29/792
摘要： A semiconductor memory device comprises a first conductivity type semiconductor region, a second conductivity type source and drain regions provided in the semiconductor region, a gate insulating film structure provided on the semiconductor region between the source region and drain region and including a first insulating film, a charge accumulation layer and a second insulating film, the charge accumulation layer being selected from a silicon nitride film, a silicon oxynitride film, an alumina film and a stacked film of these films, a control gate electrode provided on the second insulating film, a gate sidewall provided on a side of the control gate electrode and having a thickness thinner than that of the second insulating film in the center of the control gate electrode, a third insulating film provided above the control gate electrode, and a fourth insulating film provided to cover the gate electrode sidewall and the third insulating film.
摘要翻译：半导体存储器件包括第一导电型半导体区域，设置在半导体区域中的第二导电类型源极和漏极区域，设置在源极区域和漏极区域之间的半导体区域上并且包括第一绝缘膜的栅极绝缘膜结构，电荷累积层和第二绝缘膜，所述电荷累积层选自氮化硅膜，氮氧化硅膜，氧化铝膜和这些膜的堆叠膜，设置在第二绝缘膜上的控制栅电极，设置在所述控制栅电极的一侧上并且具有比所述控制栅极电极中心的所述第二绝缘膜的厚度薄的栅极侧壁，设置在所述控制栅极电极上方的第三绝缘膜，以及设置到覆盖栅电极侧壁和第三绝缘膜。

53. 发明授权

US06894931B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06894931B2
公开(公告)日：2005-05-17
申请号：US10393453
申请日：2003-03-21
申请人： Toshitake Yaegashi , Akira Goda , Mitsuhiro Noguchi
发明人： Toshitake Yaegashi , Akira Goda , Mitsuhiro Noguchi
IPC分类号： G11C16/00 , G11C16/04 , G11C16/34 , G11C16/06
CPC分类号： G11C16/0466 , G11C16/3468
摘要： A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer via a second gate insulating film. A control circuit controls the sequence of writing and erasing the data into and from a memory cell selected in the memory cell. In writing the data into the memory cell, a first write operation is to apply a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate. A second write operation is to apply a write pulse voltage with a second step-up voltage lower than the first step-up voltage.
摘要翻译：通过在半导体衬底上布置多个电可写入的可擦除非易失性存储单元来配置单元阵列。每个存储单元具有通过第一栅极绝缘膜和通过第二栅极绝缘膜在电荷累积层上形成的栅电极形成的电荷累积层。控制电路控制将数据写入和擦除存储单元中选择的存储单元的顺序。在将数据写入存储单元中，第一写入操作是在栅电极和半导体衬底之间施加具有第一升压电压的写入脉冲电压。第二写入操作是施加具有低于第一升压电压的第二升压电压的写入脉冲电压。

54. 发明申请

US20050037612A1 Superconductor device and method of manufacturing the same 失效
标题翻译：超导体装置及其制造方法
公开(公告)号：US20050037612A1
公开(公告)日：2005-02-17
申请号：US10943250
申请日：2004-09-17
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L21/8247 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/788 , H01L29/792 , H01L21/4763 , H01L21/44
CPC分类号： H01L27/11568 , H01L21/76838 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.
摘要翻译：一种半导体器件，包括形成在半导体衬底中的元件区域，嵌入在层间绝缘膜中的导体插塞和连接到插头的布线层，其中插头布置在与其中的布线层的纵向正交的直线上作为布线层的间距，使得插塞的直线和上表面彼此重叠，并且当在与基板的主表面平行的横截面中观察插塞时，并且在两个边缘点之间的距离通过每个塞子的中心的分割线通过的每个插头被定义为接触直径，接触直径具有三个或更多个最大值和三个或更多个最小值，同时分叉线在十字形中旋转截面360度。

55. 发明授权

US06819592B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06819592B2
公开(公告)日：2004-11-16
申请号：US10108574
申请日：2002-03-29
申请人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
发明人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
IPC分类号： G11C1604
CPC分类号： G11C16/26 , G11C16/0483 , H01L27/115
摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.
摘要翻译：一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导，关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

56. 发明授权

US06690047B2 MIS transistor having a large driving current and method for producing the same 失效
标题翻译：具有大驱动电流的MIS晶体管及其制造方法
公开(公告)号：US06690047B2
公开(公告)日：2004-02-10
申请号：US10132175
申请日：2002-04-26
申请人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
发明人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66621 , H01L29/78
摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
摘要翻译：在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜的高介电膜和栅电极。或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

57. 发明授权

US06169688A Magnetic storage device using unipole currents for selecting memory cells 失效
标题翻译：使用单极电流的磁存储器件用于选择存储器单元
公开(公告)号：US06169688A
公开(公告)日：2001-01-02
申请号：US09272192
申请日：1999-03-18
申请人： Mitsuhiro Noguchi
发明人： Mitsuhiro Noguchi
IPC分类号： G11C1114
CPC分类号： H01L27/228 , G11C11/15 , G11C11/16
摘要： A current flow passing a data selection line both in a data write operation and data readout operation is directed to the same direction. A soft ferromagnetic film having a coercivity smaller than that of a ferromagnetic film is formed on the ferromagnetic film via a nonmagnetic conductive film. A barrier metal layer having a projecting portion is formed on the soft ferromagnetic film. A metal conductive layer is formed at the top of the projecting portion of the barrier metal layer. An insulating interlayer is formed on the entire surface. A data selection line is formed mainly in a region where the metal conductive layer is not formed.
摘要翻译：在数据写入操作和数据读出操作中通过数据选择线的电流指向相同的方向。通过非磁性导电膜在铁磁性膜上形成矫顽力比铁磁性膜小的软磁铁膜。在软铁磁膜上形成具有突出部分的阻挡金属层。金属导电层形成在阻挡金属层的突出部分的顶部。在整个表面上形成绝缘中间层。数据选择线主要形成在未形成金属导电层的区域中。

58. 发明授权

US5969393A Semiconductor device and method of manufacture of the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5969393A
公开(公告)日：1999-10-19
申请号：US712650
申请日：1996-09-11
申请人： Mitsuhiro Noguchi
发明人： Mitsuhiro Noguchi
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/786 , H01L29/76
CPC分类号： H01L29/78696 , H01L21/76224 , H01L29/0649 , H01L29/1037 , H01L29/66575 , H01L29/66772 , H01L29/78609
摘要： A semiconductor device comprises a semiconductor substrate having a major surface, a semiconductor region defined between at least two trenches formed in the major surface, a first insulating layer formed on at least side walls of each of the trenches, and a second insulating layer formed in a predetermined area of the surface of the semiconductor region to contact the first insulating layer. The thickness of the first insulating layer at the top of the side walls is set larger than the thickness of the second insulating layer.
摘要翻译：半导体器件包括具有主表面的半导体衬底，限定在形成在主表面中的至少两个沟槽之间的半导体区域，形成在每个沟槽的至少侧壁上的第一绝缘层，以及形成在第二绝缘层中的第二绝缘层所述半导体区域的表面的预定区域与所述第一绝缘层接触。侧壁顶部的第一绝缘层的厚度被设定为大于第二绝缘层的厚度。

59. 发明授权

US08884353B2 Semiconductor memory device including a stacked gate having a charge storage layer and a control gate, and method of manufacturing the same 有权
标题翻译：包括具有电荷存储层和控制栅极的堆叠栅极的半导体存储器件及其制造方法
公开(公告)号：US08884353B2
公开(公告)日：2014-11-11
申请号：US13092662
申请日：2011-04-22
申请人： Daisuke Tsurumi , Mitsuhiro Noguchi , Haruhiko Koyama
发明人： Daisuke Tsurumi , Mitsuhiro Noguchi , Haruhiko Koyama
IPC分类号： H01L29/788 , H01L27/115 , H01L29/66 , H01L21/28 , H01L29/423
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/66825 , H01L29/788
摘要： A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.
摘要翻译：半导体存储器件包括源极区，漏极区，沟道区，电荷存储层和控制栅电极。源极区域和漏极区域在半导体衬底的表面中彼此分开地形成。沟道区形成在半导体衬底中并位于源极区和漏极区之间。电荷存储层形成在通道区域上，其间插入有第一绝缘膜。控制栅极电极形成在电荷存储层上，其间插入有第二绝缘膜。控制门具有以5nm或更大的曲率半径圆化的上角部。

60. 发明申请

US20130187208A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20130187208A1
公开(公告)日：2013-07-25
申请号：US13713341
申请日：2012-12-13
申请人： Aya Minemura , Kenji Sawamura , Mitsuhiro Noguchi
发明人： Aya Minemura , Kenji Sawamura , Mitsuhiro Noguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/76232
摘要： According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction.
摘要翻译：根据一个实施例，半导体器件包括沿着第一方向延伸的有源区域，位于有源区域的第一部分上的接触插塞和位于与有源区域中的有源区域的第一部分相邻的第二部分的晶体管第一个方向第一部分的垂直于第一方向的第二方向的顶表面积的宽度小于第二部分在第二方向上的顶表面积的宽度。

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