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51. 发明授权

US4828365A Multicolor filter for producing purer white across a display device 失效
标题翻译：用于在显示设备上生产纯白色的多色滤光片
公开(公告)号：US4828365A
公开(公告)日：1989-05-09
申请号：US158954
申请日：1988-02-22
申请人： Roger G. Stewart , Alfred C. Ipri
发明人： Roger G. Stewart , Alfred C. Ipri
IPC分类号： G02B5/20 , G02F1/1335 , G02F1/13357
CPC分类号： G02F1/133514 , G02F2201/52
摘要： A multicolor filter for a display device includes separate filter elements for individually providing the primary colors of light. The areas of the filter elements are tailored in accordance with the percentages of primary light colors in pure white light, the percentages of primary light in the illuminating source, and the light transmission capabilities of the filter elements. Additionally, the filter elements are configured so that the centroid of the filter elements are within the close proximity of a straight line passing through adjacent filter elements.

52. 发明授权

US4589008A Apparatus for electrically joining the ends of substantially parallel semiconductor lines 失效
标题翻译：用于电连接基本上平行的半导体线路的端部的装置
公开(公告)号：US4589008A
公开(公告)日：1986-05-13
申请号：US299344
申请日：1981-09-04
申请人： Roger G. Stewart , Moshe Mazin
发明人： Roger G. Stewart , Moshe Mazin
IPC分类号： G11C5/02 , H01L23/498 , H01L27/12 , H01L23/50
CPC分类号： H01L23/49872 , G11C5/025 , H01L27/12 , H01L2924/0002 , Y10S257/91 , Y10S257/926
摘要： Apparatus, comprising a series of staggered metal contacts, is used to join adjacent ends of adjacent sets of substantially parallel semiconductor lines. The lines of one set can have a conductivity type opposite that of the lines of the adjacent set. Also, one of the sets may comprise epitaxial silicon, grown on an insulating substrate such as sapphire, while the other set comprises polycrystalline silicon.
摘要翻译：包括一系列交错的金属触点的装置用于连接相邻组的基本上平行的半导体线的相邻端。一组的线可以具有与相邻组的线相反的导电类型。另外，这些组中的一个可以包括在诸如蓝宝石的绝缘衬底上生长的外延硅，而另一组包括多晶硅。

53. 发明授权

US4464755A Memory system with error detection and correction 失效
标题翻译：具有错误检测和校正的存储器系统
公开(公告)号：US4464755A
公开(公告)日：1984-08-07
申请号：US362463
申请日：1982-03-26
申请人： Roger G. Stewart , Andrew G. F. Dingwall
发明人： Roger G. Stewart , Andrew G. F. Dingwall
IPC分类号： G06F11/10
CPC分类号： G06F11/1032
摘要： A memory system comprised of M memory modules where M-1 of the modules are for storing data bits and the Mth modules is for storing system parity bits corresponding to the data bits stored in the other M-1 modules. Each module has R.multidot.C bit locations organized into W internal words of L bits and includes a parity array for storing one parity bit for each internal word, where L is greater than 1, and RC=WL. Each module includes means for reading an internal word and for reading-out a particular subset of the L bits of that internal word. Each module includes means for checking the parity of a selected internal word and for producing a first parity signal indicating whether or not it is correct. The memory system includes means for checking the parity of the selected subsets read out from the M modules and for producing a system parity signal indicating whether the parity of the M subsets is correct. When the first parity signal and the system parity signals indicate the presence of parity errors the subset read out from a module whose first parity signal indicates the presence of a parity error is corrected.
摘要翻译：一种由M个存储器模块组成的存储器系统，其中模块的M-1用于存储数据位，并且第M个模块用于存储对应于存储在其它M-1模块中的数据位的系统奇偶校验位。每个模块具有组织成L位的W个内部字的RxC位位置，并且包括用于存储每个内部字的一个奇偶校验位的奇偶校验位，其中L大于1，并且RC = WL。每个模块包括用于读取内部字和用于读出该内部字的L位的特定子集的装置。每个模块包括用于检查所选择的内部字的奇偶性并用于产生指示其是否正确的第一奇偶校验信号的装置。存储器系统包括用于检查从M个模块读出的所选择的子集的奇偶校验以及用于产生指示M个子集的奇偶校验是否正确的系统奇偶校验信号的装置。当第一奇偶校验信号和系统奇偶校验信号指示奇偶校验错误的存在时，校正从其第一奇偶校验信号指示存在奇偶校验错误的模块读出的子集。

54. 发明授权

US4442447A Electrically alterable nonvolatile floating gate memory device 失效
标题翻译：电可变非挥发性浮栅存储器件
公开(公告)号：US4442447A
公开(公告)日：1984-04-10
申请号：US472636
申请日：1983-03-07
申请人： Alfred C. Ipri , Roger G. Stewart
发明人： Alfred C. Ipri , Roger G. Stewart
IPC分类号： G11C14/00 , G11C16/04 , G11C17/00 , H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792 , H01L27/02 , G11C11/40
CPC分类号： G11C16/0416 , H01L29/7883
摘要： An electrically alterable, nonvolatile floating gate memory device is described having enhanced write efficiency by reason of an extension of the floating gate member. The extension is made to extend over the drain line of an adjacent memory device and serves to provide the floating gate member with additional capacitance during the write operation thereby permitting a higher write efficiency for a given voltage.
摘要翻译：描述了一种电气可变的非易失性浮动栅极存储器件，其通过浮动栅极部件的延伸而具有增强的写入效率。延伸部分延伸到相邻存储器件的漏极线上，并且用于在写入操作期间为浮置栅极部件提供额外的电容，从而允许给定电压的更高的写入效率。

55. 发明授权

US4423432A Apparatus for decoding multiple input lines 失效
标题翻译：多输入线路解码装置
公开(公告)号：US4423432A
公开(公告)日：1983-12-27
申请号：US299791
申请日：1981-09-04
申请人： Roger G. Stewart , Moshe Mazin
发明人： Roger G. Stewart , Moshe Mazin
IPC分类号： G11C5/02 , G11C17/18 , H01L27/12 , G11C11/40 , H01L27/00
CPC分类号： H01L27/12 , G11C17/18 , G11C5/025 , Y10S257/926
摘要： Apparatus for decoding multiple input lines includes a line selector and a line deselector. The line selector is capable of receiving a plurality of closely spaced input lines and simultaneously decoding the input lines into at least one output line having an effective pitch which can be arbitrarily greater than the pitch of the input lines. An array of MOS transistors is formed in the line selector to decode the input lines while increasing the output pitch relative to the input pitch. Similarly, the line deselector receives the same plurality of input lines and insures that deselected lines are connected to an appropriate voltage potential in order to prevent them from "floating".
摘要翻译：用于解码多个输入线的装置包括线路选择器和线路选择器。线选择器能够接收多个紧密间隔的输入线，并且同时将输入线解码为具有任意大于输入线的间距的有效间距的至少一个输出线。在线选择器中形成MOS晶体管阵列，以便在输入线路相对于输入节距增加输出线的同时解码输入线。类似地，线路选择器接收相同的多条输入线，并确保取消选择的线路连接到适当的电压电位，以防止它们“浮动”。

56. 发明授权

US4398102A Gated parallel decoder 失效
标题翻译：门控并行解码器
公开(公告)号：US4398102A
公开(公告)日：1983-08-09
申请号：US232302
申请日：1981-02-06
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G11C11/413 , G11C11/41 , H03K19/017 , H03K19/0948 , H03K19/096 , G11C8/00 , H03K19/094
CPC分类号： H03K19/01742 , H03K19/01721 , H03K19/0948 , H03K19/0963
摘要： The decoder includes a plurality of input signal responsive transistors having their conduction paths connected in parallel between a node and a point of reference potential. These transistors, when turned-on, tend to clamp the node to the reference potential. A controllable load is connected between a second voltage and the node for, when enabled and in the absence of an inhibit signal, providing a conduction path charging the node towards the second voltage. An inhibit network responsive to the node voltage inhibits conduction via the charging conduction path of the load when the node voltage is at, or close to, the second voltage. An external control signal applied to the controllable load can enable it in the absence of the inhibit signal.
摘要翻译：解码器包括多个输入信号响应晶体管，其导通路径并联连接在节点和参考点之间。这些晶体管在导通时倾向于将节点钳位到参考电位。可控负载连接在第二电压和节点之间，用于当使能并且在没有禁止信号时，提供将节点充电到第二电压的导电路径。当节点电压处于或接近第二电压时，响应于节点电压的禁止网络经由负载的充电传导路径禁止传导。施加到可控负载的外部控制信号可以在没有禁止信号的情况下使其能够使能。

57. 发明授权

US4216390A Level shift circuit 失效
标题翻译：电平移位电路
公开(公告)号：US4216390A
公开(公告)日：1980-08-05
申请号：US948509
申请日：1978-10-04
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G11C11/34 , G11C11/4093 , G11C16/12 , H03K3/356 , H03K5/02 , H03K3/353 , H03K17/10
CPC分类号： G11C16/12 , G11C11/4093 , H03K3/356147 , H03K5/023
摘要： A gating means, biased to pass current only during signal transitions, transfers binary signals from an input signal source to a latch circuit when the signal source and the latch are operated at similar voltages. Following data transfer, the operating voltage across the latch is increased. The voltage levels of the latch output signals are correspondingly increased but the state to which the latch was set is maintained and there is no steady state current conduction through the gating means.
摘要翻译：当信号源和锁存器在相似的电压下工作时，仅在信号转换期间偏置以通过电流的选通装置将二进制信号从输入信号源传送到锁存电路。在数据传输之后，锁存器上的工作电压增加。闩锁输出信号的电压电平相应地增加，但是保持锁存器设置的状态，并且通过门控装置没有稳态电流传导。

58. 发明申请

US20110122718A1 Low Cost Testing and Sorting for Integrated Circuits 有权
标题翻译：集成电路的低成本测试和排序
公开(公告)号：US20110122718A1
公开(公告)日：2011-05-26
申请号：US12328675
申请日：2008-12-04
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G11C29/38 , H01L21/66
CPC分类号： G11C29/006 , G11C29/38 , G11C2029/4002
摘要： Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second non-volatile memory. An integrated circuit is independently functional upon separation from the cluster if the codes in the first and second non-volatile memories match. Upon separation, integrated circuits are queried to determine which respond. Each integrated circuit includes logic adapted to determine whether the codes in the first and second non-volatile memories match. If the codes do not match, the logic permanently disables the integrated circuit upon separation from the cluster.
摘要翻译：公开了集群中集成电路的测试和分类方法。每个集群的电源和数据终端连接到公共电源和数据总线，提供公共电源。每个集成电路具有存储激活码的第一非易失性存储器和能够存储激活码的第二可编程非易失性存储器。如果集成电路通过测试，则将存储在第一非易失性存储器中的激活码写入第二非易失性存储器。如果第一和第二非易失性存储器中的代码匹配，则与集群分离时，集成电路是独立的。分离后，查询集成电路以确定哪些响应。每个集成电路包括适于确定第一和第二非易失性存储器中的代码是否匹配的逻辑。如果代码不匹配，则与集群分离时，逻辑将永久禁用集成电路。

59. 发明申请

US20080197981A1 INTEGRATED CIRCUITS WITH PERSISTENT DATA STORAGE 有权
标题翻译：具有持续数据存储的集成电路
公开(公告)号：US20080197981A1
公开(公告)日：2008-08-21
申请号：US12111140
申请日：2008-04-28
申请人： Roger G. Stewart , John Rolin
发明人： Roger G. Stewart , John Rolin
IPC分类号： H04B1/713
CPC分类号： G06K19/0723 , G06K7/10019 , G06K19/07381
摘要： The circuitry introduced in this invention selectively slows down the functioning of an electronic circuit maintaining a particular state for a prolonged period of time. This circuitry is used not only to achieve the desired effect in maintaining security from electronic thieves trying to circumvent codes but also in other applications such as enabling a circuit to continue to function in the event of a brief loss of power. For example, in an RFID system, if a reader is frequency hopping, a tag loses power for as long as about 400 milliseconds when the reader changes to other frequencies. In a preferred embodiment, the disclosed circuitry is used in conjunction with a destruct sequence.
摘要翻译：在本发明中引入的电路选择性地减慢保持特定状态长时间的电子电路的功能。该电路不仅用于在维护电子窃贼试图绕过代码的安全性方面实现期望的效果，而且在其他应用中，例如使电路在短暂的功率损失的情况下继续工作。例如，在RFID系统中，如果读取器跳频，当读取器改变到其他频率时，标签失去长达约400毫秒的功率。在优选实施例中，所公开的电路与破坏序列结合使用。

60. 发明授权

US07262686B2 Methods and apparatuses to identify devices 有权
标题翻译：识别设备的方法和设备
公开(公告)号：US07262686B2
公开(公告)日：2007-08-28
申请号：US11132085
申请日：2005-05-17
申请人： Roger G. Stewart , John Stephen Smith
发明人： Roger G. Stewart , John Stephen Smith
IPC分类号： H04Q5/22 , G09F9/30 , G08B3/00
CPC分类号： G06K7/10049 , G06K7/0008 , G06K7/08
摘要： A reader identifies tags without requiring or determining whether a response to an interrogation was a single response from a single tag or multiple responses from multiple tags. A method is performed by a tag in an identification system, and the method includes receiving a first data from a reader, and correlating the first data with a first corresponding portion of the tag's identification code, and specifying a match if the first data matches the first corresponding portion, and receiving second data which, combined with the first data, is correlated with a second corresponding portion of the tag's identification code.
摘要翻译：读者识别标签，而不需要或确定对询问的响应是来自单个标签的单个响应还是来自多个标签的多个响应。一种方法由识别系统中的标签执行，该方法包括从读取器接收第一数据，并将第一数据与标签的识别码的第一对应部分相关联，并且如果第一数据与第一数据匹配，则指定匹配第一对应部分，以及接收与第一数据组合的第二数据与标签的识别码的第二对应部分相关联。

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