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51. 发明授权

US06555453B1 Fully nickel silicided metal gate with shallow junction formed 有权
标题翻译：全镍硅化金属栅极，形成浅结
公开(公告)号：US06555453B1
公开(公告)日：2003-04-29
申请号：US10058219
申请日：2002-01-29
申请人： Qi Xiang , Christy Mei-Chu Woo , George J. Kluth
发明人： Qi Xiang , Christy Mei-Chu Woo , George J. Kluth
IPC分类号： H01L2128
CPC分类号： H01L29/66507 , H01L21/2257 , H01L21/28097 , H01L21/28518 , H01L29/41783 , H01L29/4975 , H01L29/6659
摘要： Semiconductor devices having fully metal silicided gate electrodes, and methods for making the same, are disclosed. The devices have shallow S/D extensions with depths of less than about 500 Å. The methods for making the subject semiconductor devices employ diffusion of dopant from metal suicides to form shallow S/D extensions, followed by high energy implantation and activation, and metal silicidation to form S/D junctions having metal silicide connect regions and a fully metal silicided electrode.
摘要翻译：公开了具有完全金属硅化物栅电极的半导体器件及其制造方法。这些器件具有深度小于约500的浅的S / D延伸。制造本发明的半导体器件的方法是使用掺杂剂从金属硅化物扩散以形成浅的S / D扩展，接着是高能量注入和激活，以及金属硅化以形成具有金属硅化物连接区域和全金属硅化物的S / D结电极。

52. 发明授权

US06545370B1 Composite silicon nitride sidewall spacers for reduced nickel silicide bridging 有权
标题翻译：用于还原硅化镍桥接的复合氮化硅侧壁间隔物
公开(公告)号：US06545370B1
公开(公告)日：2003-04-08
申请号：US09679375
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser
IPC分类号： H01L27088
CPC分类号： H01L29/665 , H01L29/4983 , H01L29/6656
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by employing composite silicon nitride sidewall spacers comprising an outer layer having reduced free silicon. Embodiments include forming composite silicon nitride sidewall spacers comprising an inner silicon nitride layer, having a refractive index of about 1.95 to about 2.05 and a thickness of about 450 Å to about 550 Å, on the side surfaces of the gate electrode and an outer silicon nitride layer, having a refractive index to less than about 1.95 and a thickness of about 350 Å to about 450 Å.
摘要翻译：通过使用复合氮化硅侧壁间隔物来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接，所述复合氮化硅侧壁间隔物包括具有减少的自由硅的外层。实施例包括形成复合氮化硅侧壁间隔物，其包括内部氮化硅层，折射率为约1.95至约2.05，厚度约为450至大约的厚度在栅电极和外部氮化硅层，具有小于约1.95的折射率和约350至约的厚度。

53. 发明授权

US06541866B1 Cobalt barrier for nickel silicidation of a gate electrode 有权
标题翻译：用于栅电极的镍硅化的钴屏障
公开(公告)号：US06541866B1
公开(公告)日：2003-04-01
申请号：US09778113
申请日：2001-02-07
申请人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George J. Kluth
发明人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George J. Kluth
IPC分类号： H01L2348
CPC分类号： H01L21/28052 , H01L29/4941
摘要： Nickel silicidation of a gate electrode is controlled using a cobalt barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of cobalt thereon and an upper polycrystalline silicon layer on the cobalt layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel suicide and a cobalt silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.
摘要翻译：使用钴阻挡层控制栅电极的镍硅化。实施例包括形成包括下多晶硅层，钴层上的钴层和钴层上的上多晶硅层的栅电极结构，沉积镍层和硅化物，由此将上多晶硅层转化为硅化镍，形成防止镍与下部多晶硅层反应的硅化钴阻挡层。

54. 发明授权

US06541860B1 Barrier-to-seed layer alloying in integrated circuit interconnects 失效
标题翻译：集成电路互连中的屏蔽到种子层合金化
公开(公告)号：US06541860B1
公开(公告)日：2003-04-01
申请号：US09875457
申请日：2001-06-05
申请人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Joffre F. Bernard
发明人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Joffre F. Bernard
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76855 , H01L21/76858 , H01L21/76873 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and a method for manufacture thereof are provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. An opening is formed in the dielectric layer. A barrier layer with an alloying element is deposited to line the opening in the dielectric layer. A conductor core is deposited on the barrier layer to fill the opening and connect to the semiconductor device. The conductor core is annealed causing migration of the alloy element into the conductor core.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层。在电介质层中形成开口。沉积具有合金元素的阻挡层以使介电层中的开口线对齐。导体芯沉积在阻挡层上以填充开口并连接到半导体器件。导体芯退火，导致合金元件迁移到导体芯中。

55. 发明授权

US06509267B1 Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer 失效
标题翻译：在无电镀铜种子层的低k互连上形成低电阻势垒的方法
公开(公告)号：US06509267B1
公开(公告)日：2003-01-21
申请号：US09884058
申请日：2001-06-20
申请人： Christy Mei-Chu Woo , Suzette K. Pangrle , Connie Pin-Chin Wang
发明人： Christy Mei-Chu Woo , Suzette K. Pangrle , Connie Pin-Chin Wang
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76832 , H01L21/76846 , H01L21/76873
摘要： A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate. The second metal layer serves as a nucleation step for electrolessly plating a copper seed layer.
摘要翻译：用于形成金属互连结构的方法在电介质层的图案化开口内提供诸如氮化物之类的阻挡材料的共形层。在将开口蚀刻到电介质层上之后，阻挡材料沉积，停止在扩散阻挡层上。诸如钽的金属阻挡材料的第一层被共形沉积在阻挡材料上。执行定向蚀刻，其去除水平氮化物和钽，留下图案化开口的侧壁上的氮化物和钽。阻挡材料在覆盖导电材料的扩散阻挡层的蚀刻期间以及在随后的溅射蚀刻清洁期间防止介电层从导电材料（例如铜）中的污染。薄的第二金属层被共形沉积，并且在开口的侧壁上形成合适的阻挡层，同时在第二金属层和下面的基底之间提供低的接触电阻。第二金属层用作无机电镀铜籽晶层的成核步骤。

56. 发明授权

US06506668B1 Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability 有权
标题翻译：利用退火增强或修复种子层以提高铜互连的可靠性
公开(公告)号：US06506668B1
公开(公告)日：2003-01-14
申请号：US09887148
申请日：2001-06-22
申请人： Christy Mei-Chu Woo , Connie Pin-Chin Wang , Steve C. Avanzino
发明人： Christy Mei-Chu Woo , Connie Pin-Chin Wang , Steve C. Avanzino
IPC分类号： H01L213205
CPC分类号： H01L21/76843 , C25D7/123 , H01L21/76858 , H01L21/76864 , H01L21/76868 , H01L21/76873 , H01L21/76877 , H01L21/76883 , H01L2221/1089
摘要： A method of forming interconnects on a semiconductor chip is disclosed which comprises the steps of: depositing a barrier layer and a copper seed layer on the semiconductor chip; depositing on the copper seed layer an enhancement layer; annealing the semiconductor chip a first time after the copper seed layer and the enhancement layer are deposited to form an annealed layer; electroplating a copper layer on the semiconductor chip; and annealing the semiconductor chip a second time after the copper layer is deposited on the annealed layer to form an annealed copper conductive layer.
摘要翻译：公开了一种在半导体芯片上形成互连的方法，其包括以下步骤：在半导体芯片上沉积阻挡层和铜籽晶层; 在铜籽晶层上沉积增强层; 在沉积铜籽晶层和增强层之后，首先退火半导体芯片，形成退火层; 在半导体芯片上电镀铜层; 并且在铜层沉积在退火层上之后第二次对半导体芯片退火以形成退火的铜导电层。

57. 发明授权

US06441490B1 Low dielectric constant stop layer for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的低介电常数阻挡层
公开(公告)号：US06441490B1
公开(公告)日：2002-08-27
申请号：US09774849
申请日：2001-01-30
申请人： Minh Van Ngo , Christy Mei-Chu Woo
发明人： Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L2940
CPC分类号： H01L23/5329 , H01L21/76807 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口和填充沟道开口的导体芯。在通道电介质层上形成通孔停止层，使氢浓度低于15原子％，并且在通孔停止层上方形成通孔电介质层，并具有通孔。通孔电介质层上的第二通道介电层具有第二通道开口。填充第二通道开口和通孔开口的第二导体芯连接到半导体器件。

58. 发明授权

US06402909B1 Plating system with shielded secondary anode for semiconductor manufacturing 有权
标题翻译：具有半导体制造屏蔽二次阳极的电镀系统
公开(公告)号：US06402909B1
公开(公告)日：2002-06-11
申请号：US09678504
申请日：2000-10-02
申请人： Minh Quoc Tran , Christy Mei-Chu Woo
发明人： Minh Quoc Tran , Christy Mei-Chu Woo
IPC分类号： C25D1700
CPC分类号： C25D17/001 , C25D7/123 , Y10S204/07
摘要： An electroplating system is provided for semiconductor wafers which include a plating chamber having a consumable shielded secondary anode shielded by an inert anode from a semiconductor wafer connector. For a copper plating system the plating chamber has a consumable copper shielded anode shielded by an inert platinum anode from a semiconductor wafer connector.
摘要翻译：为半导体晶片提供电镀系统，其包括具有由半导体晶片连接器被惰性阳极屏蔽的消耗屏蔽二次阳极的电镀室。对于镀铜系统，电镀室具有由半导体晶片连接器的惰性铂阳极屏蔽的消耗铜屏蔽阳极。

59. 发明授权

US06383880B1 NH3/N2-plasma treatment for reduced nickel silicide bridging 有权
标题翻译： NH3 / N2等离子体处理用于还原硅化镍桥接
公开(公告)号：US06383880B1
公开(公告)日：2002-05-07
申请号：US09679374
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Robert A. Huertas
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Robert A. Huertas
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/3105
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen to create a clean surface region having increased nitrogen. Embodiments include treating the silicon nitride sidewall spacers with an ammonia and nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译：通过用包含氨和氮的等离子体处理氮化硅侧壁间隔物的暴露表面以产生具有增加的氮的清洁表面区域来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源/漏区之间的桥接。实施例包括用氨和氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

60. 发明授权

US06372673B1 Silicon-starved nitride spacer deposition 有权
标题翻译：缺硅氮化物间隔物沉积
公开(公告)号：US06372673B1
公开(公告)日：2002-04-16
申请号：US09781256
申请日：2001-02-13
申请人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
发明人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
IPC分类号： H01L21318
CPC分类号： H01L29/665 , H01L21/3185
摘要： Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.
摘要翻译：通过形成具有基本上没有或显着减少的Si的硅绝缘氮化硅侧壁间隔物来避免金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的桥接，可用于与沉积金属反应，例如镍。

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