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51. 发明授权

US06396112B2 Method of fabricating buried source to shrink chip size in memory array 有权
标题翻译：在存储器阵列中制造掩埋源以收缩芯片尺寸的方法
公开(公告)号：US06396112B2
公开(公告)日：2002-05-28
申请号：US09784824
申请日：2001-02-20
申请人： Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
发明人： Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
IPC分类号： H01L2978
CPC分类号： H01L29/0847 , H01L21/76895 , H01L27/1052 , H01L27/112 , H01L29/0649 , H01L29/66636
摘要： A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.
摘要翻译：提供一种用于在半导体器件中形成掩埋源极线的方法。在本领域中已知在半导体衬底的表面上形成掩埋触点。本发明公开了一种制造半导体器件的方法，特别是具有埋入衬底内的源极区和源极线两者的存储单元。源极线形成在源极区域上的衬底中的沟槽中。沟槽壁增强了电压抗穿透保护。沟槽还提供了延伸的侧壁区域，较小的薄层电阻以及更小的单元面积，因此，更小的芯片尺寸和更快的访问时间，如本发明的实施例所要求的优点。这里公开的掩埋源与源极线集成，该源极线也被埋在衬底内。

52. 发明授权

US06385089B2 Split-gate flash cell for virtual ground architecture 有权
标题翻译：分体式闪存单元，用于虚拟地面架构
公开(公告)号：US06385089B2
公开(公告)日：2002-05-07
申请号：US09851215
申请日：2001-05-08
申请人： Hung-Cheng Sung , Din-Son Kuo , Chia-Ta Hsieh , Yai-Fen Lin
发明人： Hung-Cheng Sung , Din-Son Kuo , Chia-Ta Hsieh , Yai-Fen Lin
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory.
摘要翻译：在本发明中，位线被离子注入到闪存单元阵列的浮置栅极旁边的列中的半导体衬底中。控制栅极叠加每行浮动栅极，并作为闪存单元行的字线工作。每个位线用于为一个单元提供漏极和用于相邻单元的源的双重目的。闪存单元被编程，擦除和读取，这取决于施加到掩埋位线的电压和构成为延伸每行的长度的控制栅极的字线。通过将位线注入到半导体衬底中，可以使闪存单元更小以改善闪存的密度。

53. 发明授权

US06380035B1 Poly tip formation and self-align source process for split-gate flash cell 失效
标题翻译：分离栅闪光单元的多尖端形成和自对准源工艺
公开(公告)号：US06380035B1
公开(公告)日：2002-04-30
申请号：US09713806
申请日：2000-11-16
申请人： Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh , Yai-Fen Lin
发明人： Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh , Yai-Fen Lin
IPC分类号： H01L21336
CPC分类号： H01L27/11519 , H01L21/28273 , H01L27/11521 , H01L29/42324
摘要： A novel method of forming a polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notched nitride layer over the tip. At the same time, a method of forming a self-aligned source (SAS) line is disclosed. A relatively thin polygate is formed so as to decrease the growth of the protrusion of conventional gate bird's beak (GBB) to a smaller and sharper tip. It will be known by those skilled in the art that GBB is easily damaged during conventional poly etching where polyoxide is used as a hard mask. To use polyoxide as a hard mask, thick polysilicon is needed in the first place. Such thick poly will increase gate coupling ratio, which has the attendant effect of degrading program and erasing performance of the memory cell. Furthermore, as the cell size is being scaled down, poly oxidation is getting, to be a difficult process due to oxide thinning effect, unless a protective measure is undertaken as disclosed in this invention. Finally, with the disclosed smaller poly tip of this invention in comparison with the GBB of prior art, the smaller is the encroachment under the polysilicon edge, and hence the smaller is the impact on the electric-field intensity between the corner edge of the floating gate and the control gate of the completed cell structure, and thus faster is the memory speed.
摘要翻译：公开了一种用于形成分支栅闪存单元中用于增强的F-N隧穿的多晶硅栅尖（poly tip）的新方法。通过在尖端上形成切口的氮化物层来进一步增强多晶硅尖端。同时，公开了一种形成自对准源（SAS）线的方法。形成相对薄的多孔，以便将常规门鸟嘴（GBB）的突起的生长减小到更小和更尖锐的尖端。本领域技术人员将知道，在使用多氧化物作为硬掩模的常规聚蚀刻中，GBB容易损坏。为了使用聚氧化物作为硬掩模，首先需要厚多晶硅。这种厚多晶硅会增加栅极耦合比，这具有降低程序和擦除存储单元性能的效果。此外，随着电池尺寸的缩小，除了如本发明所公开的保护措施之外，聚氧化物由于氧化物变薄效应而变得困难。最后，与现有技术的GBB相比，本发明公开的较小的多头尖端，多晶硅边缘下的侵入越小，因此对浮动的角边缘之间的电场强度的影响越小门和控制门的完整单元结构，因此内存速度更快。

54. 发明授权

US06309928B1 Split-gate flash cell 有权
标题翻译：分离式闪存单元
公开(公告)号：US06309928B1
公开(公告)日：2001-10-30
申请号：US09208913
申请日：1998-12-10
申请人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
发明人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76895 , H01L21/76897 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F—N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.
摘要翻译：公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

55. 发明授权

US06277686B1 PIP capacitor for split-gate flash process 有权
公开(公告)号：US06277686B1
公开(公告)日：2001-08-21
申请号：US09347546
申请日：1999-07-06
申请人： Chung-Ker Yeh , Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh , Yai-Fen Lin
发明人： Chung-Ker Yeh , Hung-Cheng Sung , Di-Son Kuo , Chia-Ta Hsieh , Yai-Fen Lin
IPC分类号： H01L218242
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11531
摘要： A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, respectively, of the split-gate flash memory cell. Furthermore, the thin interpoly oxide of the cell, rather than the thick poly-oxide over the floating gate is used as the insulator between the plates of the capacitor. The resulting capacitor yields high storage capacity through high capacitance per unit area.

56. 发明授权

US06242308B1 Method of forming poly tip to improve erasing and programming speed split gate flash 有权
标题翻译：形成多头尖端的方法，以改善擦除和编程速度分流闸闪光
公开(公告)号：US06242308B1
公开(公告)日：2001-06-05
申请号：US09354671
申请日：1999-07-16
申请人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
发明人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
IPC分类号： H01L218247
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： A method is disclosed for forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve the erasing and programming speed of the cell. The method involves the use of an oxide other than the poly oxide that is conventionally employed in forming the floating gate, and also using to advantage a so-called “smiling effect” which is normally taught away. The smiling effect, or an uneven thickening of an oxide layer, comes into play while growing interpoly oxide where concurrently the oxidation of the polysilicon gate advances in such a manner so as to form a sharp and reliable poly tip. The invention is also directed to providing a split gate flash memory cell having a thin floating gate and a poly tip therein.
摘要翻译：公开了一种用于形成具有薄浮动栅极和尖锐多晶硅尖端的分裂栅极快闪存储器单元的方法，以便提高电池的擦除和编程速度。该方法包括使用通常用于形成浮动栅极的多晶氧化物以外的氧化物，并且还利用通常被教导的所谓的“微笑效果”。微生物效应或氧化物层的不均匀增厚在生长多晶氧化物的同时发生，同时多晶硅栅极的氧化同时进行以形成尖锐且可靠的多晶硅尖端。本发明还涉及提供一种具有薄的浮动栅极和多个尖端的分裂栅极闪存单元。

57. 发明授权

US06229176B1 Split gate flash with step poly to improve program speed 有权
标题翻译：分步灯闪光与步骤多，以提高程序速度
公开(公告)号：US06229176B1
公开(公告)日：2001-05-08
申请号：US09257833
申请日：1999-02-25
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-Ke Yeh , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-Ke Yeh , Di-Son Kuo
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.
摘要翻译：提供了一种用于形成分支栅极快闪存储器单元的方法，其具有支撑不同厚度的多晶硅氧化物的台阶聚合物，以改善电池的全部性能。多晶氧化物形成在第一多晶硅层的部分上，该第一多晶硅层又被部分蚀刻以形成邻近聚氧化物下面的浮动栅极的侧壁的台阶。接着在步骤poly上由热的温度氧化物形成间隔物。然后形成间极氧氮化物，并且控制栅极被图案化与浮置栅极与介入的多晶硅氧化物重叠。步进多晶硅和间隔件在控制栅极和浮动栅极之间形成适当的距离，同时保持多晶硅尖端和控制栅极之间的距离不变，使得控制栅极和浮动栅极之间以及浮动栅极和浮动栅极之间的适当耦合实现了衬底，从而改进了具有阶梯聚光的分离栅极闪存的全部性能。

58. 发明授权

US06228695B1 Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate 有权
标题翻译：用自对准源和自对准浮栅制作分闸的控制门的方法
公开(公告)号：US06228695B1
公开(公告)日：2001-05-08
申请号：US09320759
申请日：1999-05-27
申请人： Chia-Ta Hsieh , Hung-Cheng Sung , Yai-Fen Lin , Jack Yeh , Di-Son Kuo
发明人： Chia-Ta Hsieh , Hung-Cheng Sung , Yai-Fen Lin , Jack Yeh , Di-Son Kuo
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by depositing a poly-2 layer to form a spacer floating gate adjacent to the control gate with an intervening intergate oxide layer. The source is self-aligned and the floating gate is also formed to be self-aligned to the control gate, thus making it possible to reduce the cell size. The resulting self-aligned source alleviates punch-through from source to control gate while the self-aligned floating gate with respect to the control gate provides improved programmability. The method also replaces the conventional poly oxidation process thereby yielding improved sharp peak of floating gate for improved erasing and writing of the split-gate flash memory cell.
摘要翻译：公开了一种具有自对准源和对准控制栅极的浮置栅极的分裂栅极闪存单元及其形成方法。这通过在硅衬底上的栅极氧化物层上沉积多晶层来实现，以形成垂直控制栅极，随后沉积多晶硅层以形成与控制栅极相邻的间隔物浮动栅极，其中间隔栅极氧化层。源极是自对准的，并且浮栅也形成为与对栅极自对准，从而可以减小电池的尺寸。所产生的自对准源减轻了从源极到控制栅极的穿通，而相对于控制栅极的自对准浮动栅极提供了改进的可编程性。该方法也取代了传统的多晶氧化工艺，从而产生改善的浮栅的尖峰，以改善分离栅闪存单元的擦除和写入。

59. 发明授权

US06180977B2 Self-aligned edge implanted cell to reduce leakage current and improve program speed in split-gate flash 有权
标题翻译：自对准边缘植入电池，以减少漏电流并提高分闸门闪存中的编程速度
公开(公告)号：US06180977B2
公开(公告)日：2001-01-30
申请号：US09389631
申请日：1999-09-03
申请人： Yai-Fen Lin , Hung-Cheng Sung , Chia-Ta Hsieh , Di-Son Kuo
发明人： Yai-Fen Lin , Hung-Cheng Sung , Chia-Ta Hsieh , Di-Son Kuo
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method is provided for fabricating a self-aligned edge implanted split-gate flash memory comprising a semiconductor substrate of a first conductivity type having separated first and second regions of a second conductivity type formed therein, the first and second regions defining a substrate channel region therebetween; a floating gate separated from a doped region in the substrate by an oxide layer; a control gate partially overlying and separated by an insulator from said floating gate; said floating gate having thin portions and thick portions; and said thin portions of said floating gate overlying twice doped regions in said semiconductor substrate to reduce surface leakage current and improve program speed of the memory cell.
摘要翻译：提供了一种用于制造自对准边缘注入分裂栅极闪存的方法，该闪存包括形成有分离的第二和第二区域的第一导电类型的半导体衬底，第一和第二区域限定衬底沟道区域之间; 通过氧化物层与衬底中的掺杂区域分离的浮置栅极; 由所述浮动栅极部分地由绝缘体覆盖并分离的控制栅极; 所述浮栅具有薄部分和厚部分; 并且所述浮动栅极的所述薄部分覆盖所述半导体衬底中的两个掺杂区域，以减少表面泄漏电流并提高存储器单元的编程速度。

60. 发明授权

US6159801A Method to increase coupling ratio of source to floating gate in split-gate flash 有权
公开(公告)号：US6159801A
公开(公告)日：2000-12-12
申请号：US298932
申请日：1999-04-26
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7885
摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

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