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51. 发明申请

US20050045995A1 Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations 有权
标题翻译：超薄绝缘体上硅和具有混合晶体取向的应变硅绝缘体
公开(公告)号：US20050045995A1
公开(公告)日：2005-03-03
申请号：US10932982
申请日：2004-09-02
申请人： Meikei Ieong , Min Yang
发明人： Meikei Ieong , Min Yang
IPC分类号： H01L21/336 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/04 , H01L29/10 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76278 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/78654 , H01L29/78684
摘要： The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer. A semiconductor material is epitaxial grown in the opening and then various etching and etch back processing steps are used in forming the SOI substrate.
摘要翻译：本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供最佳性能。具体地说，一种集成半导体结构，其至少包括具有第一结晶取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的并且具有与顶部基本相同的厚度半导体层和第一晶体取向与第二晶体取向不同。通过将开口形成为至少包括具有不同晶体取向的第一半导体层和第二半导体层的结构，形成SOI衬底。开口延伸到第一半导体层。半导体材料在开口中外延生长，然后在形成SOI衬底中使用各种蚀刻和回蚀加工步骤。

52. 发明授权

US09355887B2 Dual trench isolation for CMOS with hybrid orientations 有权
标题翻译：具有混合取向的CMOS的双沟槽隔离
公开(公告)号：US09355887B2
公开(公告)日：2016-05-31
申请号：US13349203
申请日：2012-01-12
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L21/70 , H01L21/762
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

53. 发明授权

US07691688B2 Strained silicon CMOS on hybrid crystal orientations 失效
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US07691688B2
公开(公告)日：2010-04-06
申请号：US12143912
申请日：2008-06-23
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

54. 发明授权

US07482216B2 Substrate engineering for optimum CMOS device performance 失效
标题翻译：基板工程，实现最佳的CMOS器件性能
公开(公告)号：US07482216B2
公开(公告)日：2009-01-27
申请号：US11474774
申请日：2006-06-26
申请人： Victor W. C. Chan , Meikei Ieong , Min Yang
发明人： Victor W. C. Chan , Meikei Ieong , Min Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807
摘要： An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a direction and the at least one NFET has a current flow in a direction. The direction is perpendicular to the direction. A method of fabricating such as integrated semiconductor structure is also provided.
摘要翻译：提供了位于半导体衬底顶部的具有不同类型的互补金属氧化物半导体器件（CMOS）即PFET和NFET的集成半导体结构，其中每个CMOS器件被制造成使得每个器件的电流是最佳的。具体地，该结构包括具有（110）表面取向的半导体衬底和指向电流<001>方向的凹口; 以及位于半导体衬底上的至少一个PFET和至少一个NFET。所述至少一个PFET具有沿<110>方向的电流，并且所述至少一个NFET具有沿<100>方向的电流。 <110>方向垂直于<100>方向。还提供了诸如集成半导体结构的制造方法。

55. 发明授权

US07462525B2 Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain 有权
标题翻译：在双轴压缩应变下，增强了<110> Si中的电子和空穴迁移率
公开(公告)号：US07462525B2
公开(公告)日：2008-12-09
申请号：US11924024
申请日：2007-10-25
申请人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.
摘要翻译：本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。本发明的另一方面涉及形成本发明的半导体材料的方法。本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

56. 发明授权

US07402466B2 Strained silicon CMOS on hybrid crystal orientations 有权
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US07402466B2
公开(公告)日：2008-07-22
申请号：US11492271
申请日：2006-07-25
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

57. 发明申请

US20080044987A1 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN 审中-公开
公开(公告)号：US20080044987A1
公开(公告)日：2008-02-21
申请号：US11924015
申请日：2007-10-25
申请人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/20
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

58. 发明申请

US20080036028A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 审中-公开
公开(公告)号：US20080036028A1
公开(公告)日：2008-02-14
申请号：US11877048
申请日：2007-10-23
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L29/00 , H01L21/76 , H01L21/8238
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

59. 发明申请

US20080020521A1 HYBRID SUBSTRATE TECHNOLOGY FOR HIGH-MOBILITY PLANAR AND MULTIPLE-GATE MOSFETS 有权
标题翻译：混合基板技术用于高移动平面和多栅极MOSFET
公开(公告)号：US20080020521A1
公开(公告)日：2008-01-24
申请号：US11866786
申请日：2007-10-03
申请人： Bruce Doris , Meikei Ieong , Edward Nowak , Min Yang
发明人： Bruce Doris , Meikei Ieong , Edward Nowak , Min Yang
IPC分类号： H01L21/84
CPC分类号： H01L21/76251 , H01L21/76243 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/785
摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.
摘要翻译：提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

60. 发明申请

US20070269945A1 STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PERFORMANCE HYBRID-ORIENTATION SILICON-ON-INSULATOR CMOS DEVICES 有权
标题翻译：用于高性能混合导电硅绝缘体CMOS器件的混合基板的结构和方法
公开(公告)号：US20070269945A1
公开(公告)日：2007-11-22
申请号：US11830489
申请日：2007-07-30
申请人： Meikei Ieong , Min Yang
发明人： Meikei Ieong , Min Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207 , Y10S438/973
摘要： The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.
摘要翻译：本发明提供了一种集成半导体器件的方法，使得在混合基板的特定晶体取向上形成不同类型的器件，其增强了每种器件的性能。具体地，本发明提供了一种集成半导体器件的方法，使得pFET位于（110）晶面上，而nFET位于平面混合衬底的（100）晶面上。本发明的方法还通过埋层绝缘体和反掺杂层的组合来改进制造SOI类器件的性能。本发明还涉及利用本发明的方法形成的半导体结构。

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