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51. 发明申请

US20090197382A1 MULTI-GATED, HIGH-MOBILITY, DENSITY IMPROVED DEVICES 失效
标题翻译：多层，高移动，密度改进的设备
公开(公告)号：US20090197382A1
公开(公告)日：2009-08-06
申请号：US12023347
申请日：2008-01-31
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26546 , H01L21/26586 , H01L21/845 , H01L29/66803 , H01L29/785
摘要： Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that they are approximately perpendicular to the centerline. Then, masked implant sequences are performed, during which halo and/or source/drain dopants are implanted into the sidewalls of the semiconductor fins on one side of the chevron layout and then into the sidewalls of the semiconductor fins on the opposite side of the chevron layout. The implant direction used during these implant sequences is substantially orthogonal to the gates in order to avoid mask shadowing, which can obstruct dopant implantation when separation between the semiconductor fins in the chevron layout is scaled (i.e., when device density is increased).
摘要翻译：本文公开了在高密度，人字纹图案化的CMOS器件中形成具有高迁移率晶面的p型和n型MUGFET的改进方法的实施方案。具体地，半导体散热片形成为沿着晶片的中心线定向的人字形布局。门形成在半导体翅片附近，使得它们大致垂直于中心线。然后，进行掩蔽的植入序列，在此期间将卤素和/或源极/漏极掺杂剂注入到人字形布局的一侧上的半导体鳍片的侧壁中，然后进入人字纹相反侧的半导体鳍片的侧壁布局。在这些植入序列期间使用的植入方向基本上与栅极正交，以避免掩模阴影，当阴影布局中的半导体鳍片之间的间隔被缩放时（即，当器件密度增加时），这可能阻碍掺杂剂注入。

52. 发明申请

US20090101978A1 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法
公开(公告)号：US20090101978A1
公开(公告)日：2009-04-23
申请号：US11873521
申请日：2007-10-17
申请人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料（例如，金属硅化物）。以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

53. 发明授权

US07259590B1 Driver for multi-voltage island/core architecture 失效
标题翻译：多电压岛/核心架构驱动
公开(公告)号：US07259590B1
公开(公告)日：2007-08-21
申请号：US11276169
申请日：2006-02-16
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H03K19/0185
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.
摘要翻译：提供了一种用于为集成电路芯片的多电压岛/核心架构提供驱动器的系统和方法。互补金属氧化物半导体（CMOS）逆变器由高阈值电压p沟道场效应晶体管（hi-Vt PFET）和规则阈值电压n沟道场效应晶体管（NFET）构成，其使用最大正值电源（Vdd）在芯片上。基于最大Vdd，驱动CMOS反相器的电压岛/芯的Vdd和hi-Vt PFET的亚阈值泄漏电流要求来确定hi-Vt PFET的阈值电压。

54. 发明授权

US07087966B1 Double-Gate FETs (field effect transistors) 有权
标题翻译：双栅FET（场效应晶体管）
公开(公告)号：US07087966B1
公开(公告)日：2006-08-08
申请号：US10908583
申请日：2005-05-18
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L31/0392
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.
摘要翻译：一种半导体结构及其形成方法。该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等）。前门的宽度大于后门的宽度。前门和S / D区之间的电容小于后门和S / D区之间的电容。前门和S / D区之间的距离大于后门和S / D区之间的距离。

55. 发明授权

US08946027B2 Replacement-gate FinFET structure and process 有权
标题翻译：替代栅FinFET结构和工艺
公开(公告)号：US08946027B2
公开(公告)日：2015-02-03
申请号：US13367725
申请日：2012-02-07
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.
摘要翻译：鳍状场效应晶体管（FinFET）结构和制造FinFET的方法，其包括形成在沟道区的每个端部上的沟道区和源/漏（S / D）区的硅鳍，其中整个底表面沟道区域接触下绝缘体的顶表面，S / D区的底表面接触下硅锗（SiGe）层的顶表面的第一部分。 FinFET结构还包括接触顶部表面的外部S / D区域和下部SiGe层的顶表面的每个S / D区域和第二部分的两个侧表面。 FinFET结构还包括形成在通道区域的顶表面和两个侧表面上的适形电介质的替代栅极或栅极堆叠。

56. 发明授权

US08698245B2 Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (VT) lowering and method of forming the structure 有权
标题翻译：部分耗尽（PD）绝缘体上半导体（SOI）场效应晶体管（FET）结构，具有用于阈值电压（VT）降低的栅 - 体隧道电流区域和形成结构的方法
公开(公告)号：US08698245B2
公开(公告)日：2014-04-15
申请号：US12967329
申请日：2010-12-14
申请人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
IPC分类号： H01L27/12
CPC分类号： H01L29/78 , H01L21/26506 , H01L29/32 , H01L29/66477 , H01L29/78612
摘要： Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.
摘要翻译：公开了具有栅对体隧道电流区域（GTBTCR）的场效应晶体管的实施例和方法。在一个实施例中，具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分，以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。在另一个实施例中，半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括：与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。具有第二导电类型的栅极穿过中心部分。

57. 发明授权

US08536018B1 Maskless inter-well deep trench isolation structure and methods of manufacture 有权
标题翻译：无掩膜深沟槽隔离结构及制造方法
公开(公告)号：US08536018B1
公开(公告)日：2013-09-17
申请号：US13467314
申请日：2012-05-09
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L27/108
CPC分类号： H01L21/76283 , H01L21/76232 , H01L21/84
摘要： A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.
摘要翻译：提供了一种低功率无掩膜深沟槽隔离结构及其制造方法。一种方法包括在衬底上沉积多个层，并在多个层上形成层。该方法还包括在衬底中形成阱结构，以及在层的相对侧形成侧壁间隔物。该方法还包括通过去除侧壁间隔件和与通过去除侧壁间隔件形成的开口对准的衬底的部分，将衬底中的自对准深沟槽形成在阱结构下方。该方法还包括形成与深沟槽对准的浅沟槽。该方法还包括通过用绝缘体材料填充浅沟槽和深沟槽来形成浅沟槽隔离结构和深沟槽隔离结构。

58. 发明授权

US08378394B2 Method for forming and structure of a recessed source/drain strap for a MUGFET 有权
标题翻译：用于MUGFET的凹陷源/排水带的形成和结构的方法
公开(公告)号：US08378394B2
公开(公告)日：2013-02-19
申请号：US12876343
申请日：2010-09-07
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within the insulator layer below the fins, relative to the bottom of the structure. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap further includes recessed portions disposed within the insulator layer, below the plurality of fins, relative to the bottom of the structure, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins, relative to the bottom of the structure. The conductive strap is disposed in at least one of a source and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator.
摘要翻译：一种方法和半导体结构包括在衬底上的绝缘体层，相对于该结构的底部在绝缘体层之上的多个平行的鳍。每个翅片包括中心半导体部分和导电端部。至少一个导电带可以相对于结构的底部定位在翅片下方的绝缘体层内。导电带可以垂直于翅片并接触翅片。导电带还包括设置在绝缘体层内的凹部，相对于结构的底部在多个散热片的下方，以及设置在绝缘体层之上的每个散热片之间的突出部分，多个翅片相对于结构的底部。导电带设置在半导体结构的源极和漏极区域中的至少一个中。栅极绝缘体接触并覆盖翅片的中心半导体部分，并且栅极导体覆盖并接触栅极绝缘体。

59. 发明申请

US20120190156A1 RECESSED GATE CHANNEL WITH LOW Vt CORNER 有权
标题翻译：具有低Vt角的后门通道
公开(公告)号：US20120190156A1
公开(公告)日：2012-07-26
申请号：US13363944
申请日：2012-02-01
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/1083 , H01L29/4236 , H01L29/517 , H01L29/66621 , H01L29/78
摘要： A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.
摘要翻译：凹陷栅极FET器件包括具有上部和下部的衬底，下部具有比上部更低的掺杂剂材料的浓度; 限定周围通道区域并且具有衬底的栅介质材料层的沟槽型栅电极，并且包括具有凹陷的顶表面的导电材料，以减少相对于在上基板表面处形成的源极和漏极扩散区域的重叠电容侧电极。在栅电极的任一侧和邻接栅电极处可选地形成卤素植入物，每个卤素注入物延伸到源极和漏极扩散到沟道区域之内。此外，形成高掺杂的源极和漏极延伸区域，其提供从源极和漏极扩散区域到沟道区域的低电阻路径。

60. 发明申请

US20120146146A1 PARTIALLY DEPELETED (DP) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有门控电压（Vt）的栅极 - 体积隧道电流区域（DP）半导体绝缘体（SOI）场效应晶体管（FET）结构和形成结构的方法
公开(公告)号：US20120146146A1
公开(公告)日：2012-06-14
申请号：US12967329
申请日：2010-12-14
申请人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/26506 , H01L29/32 , H01L29/66477 , H01L29/78612
摘要： Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.
摘要翻译：公开了具有栅对体隧道电流区域（GTBTCR）的场效应晶体管的实施例和方法。在一个实施例中，具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分，以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。在另一个实施例中，半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括：与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。具有第二导电类型的栅极穿过中心部分。

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