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51. 发明授权

US07382156B2 Method and apparatus for universal program controlled bus architecture 失效
公开(公告)号：US07382156B2
公开(公告)日：2008-06-03
申请号：US11219597
申请日：2005-09-01
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17736 , H03K19/1776 , H03K19/1778 , H03K19/17796
摘要： An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.

52. 发明授权

US07368943B2 Enhanced scheme to implement an interconnection fabric using switching networks in hierarchy 有权
标题翻译：使用层次结构中的交换网络实现互连结构的增强方案
公开(公告)号：US07368943B2
公开(公告)日：2008-05-06
申请号：US11392411
申请日：2006-03-28
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H04Q3/521 , H03K17/002 , H03K19/17736 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/1332 , H04Q2213/13322
摘要： An interconnection fabric using switching networks organized in multiple levels of hierarchy to allow flexible interconnections of the switching networks amongst different levels of hierarchy and on the same level of hierarchy. The resulting interconnection fabric can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
摘要翻译：使用以多层次结构组织的交换网络的互连结构，以允许不同级别的层次结构和相同层级上的交换网络的灵活互连。所形成的互连结构可以用于诸如交换网络，路由器和可编程逻辑电路等的电子设备中。

53. 发明授权

US07126375B2 Floor plan for scalable multiple level tab oriented interconnect architecture 失效
标题翻译：可扩展多级标签定向互连架构的平面图
公开(公告)号：US07126375B2
公开(公告)日：2006-10-24
申请号：US11326543
申请日：2006-01-04
申请人： Benjamin S. Ting , Peter M. Pani
发明人： Benjamin S. Ting , Peter M. Pani
IPC分类号： G06F9/00
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17792 , H03K19/17796
摘要： A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the first level routing resources through tab networks; each tab network comprises a first plurality of switches coupling the first level routing resources to an intermediate tab and the intermediate tab coupling the second level routing resources through a second plurality of switches, each switch may comprise an additional buffer. Repeated applications of tab networks provide connections between lower level routing resources to higher level routing resources.
摘要翻译：具有逻辑块的可编程逻辑设备的多级路由架构，每个逻辑块包括多个小区，具有耦合逻辑块的小区的第一级路由资源。第二级路由资源通过标签网络耦合第一级路由资源; 每个标签网络包括将第一级路由资源耦合到中间标签的第一多个交换机，以及通过第二多个交换机耦合第二级路由资源的中间标签，每个交换机可以包括附加缓冲器。标签网络的重复应用提供了较低级别路由资源与较高级别路由资源之间的连接。

54. 发明授权

US07009422B2 Floor plan for scalable multiple level tab oriented interconnect architecture 失效
公开(公告)号：US07009422B2
公开(公告)日：2006-03-07
申请号：US10021744
申请日：2001-12-05
申请人： Benjamin S. Ting , Peter M. Pani
发明人： Benjamin S. Ting , Peter M. Pani
IPC分类号： G06F9/00
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17792 , H03K19/17796
摘要： A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit This floor plan is a scalable block architecture in which each block connector tab networks of a 2×2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions (instead of the typical north, south, east and west directions) such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4×4 block grouping to be scalable. The innovative floor plan makes efficient use of die space with little layout dead space as the floor plan provides for a plurality of contiguous memory and passgate arrays (which provide the functionality of the bidirectional switches) with small regions of logic for CFGs and drivers of the block connector tab networks. Therefore, the gaps typically incurred due to a mixture of memory and logic are avoided. Intra-cluster routing lines and bi-directional routing lines are overlayed on different layers of the chip together with memory and passgate arrays to provide connections to higher level routing lines and connections between CFGs in the block.

55. 发明授权

US06624658B2 Method and apparatus for universal program controlled bus architecture 失效
公开(公告)号：US06624658B2
公开(公告)日：2003-09-23
申请号：US10231320
申请日：2002-08-28
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H03K19177
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17736 , H03K19/1776 , H03K19/1778 , H03K19/17796
摘要： The system and method of the present invention provides an innovative bus system of lines which can be programmed and to provide data, control and address information to the logic circuits interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i.e., wide, deep or both) and the sharing of common lines for system level communication.

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