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51. 发明申请

US20080162067A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080162067A1
公开(公告)日：2008-07-03
申请号：US12043584
申请日：2008-03-06
申请人： Takashi INUKAI , Yukihiro Urakawa
发明人： Takashi INUKAI , Yukihiro Urakawa
IPC分类号： G01K15/00
CPC分类号： G01K15/002 , G01K7/425
摘要： A semiconductor integrated circuit according to the examples of the present invention is applied to a system using a first power source voltage and a second power source voltage independent of the first power source voltage and includes a first area to which the first power source voltage is supplied, a thermal sensor placed in the first area, and a first input path placed in the first area, for transferring trimming data that determine the control contents of the thermal sensor to the thermal sensor.
摘要翻译：根据本发明的实施例的半导体集成电路被应用于使用与第一电源电压无关的第一电源电压和第二电源电压的系统，并且包括提供第一电源电压的第一区域放置在第一区域中的热传感器和放置在第一区域中的第一输入路径，用于将确定热传感器的控制内容的修整数据传送到热传感器。

52. 发明申请

US20060203531A1 Method of manufacturing a semiconductor integrated circuit, a program for a computer automated design system, and a semiconductor integrated circuit 失效
标题翻译：半导体集成电路的制造方法，计算机自动化设计系统的程序以及半导体集成电路
公开(公告)号：US20060203531A1
公开(公告)日：2006-09-14
申请号：US11354958
申请日：2006-02-16
申请人： Naoyuki Tamura , Yukihiro Urakawa
发明人： Naoyuki Tamura , Yukihiro Urakawa
IPC分类号： G11C5/06
CPC分类号： H01L21/76838
摘要： A method for manufacturing a semiconductor integrated circuit uses layout data designed by a sequence of processes. The sequence of processes includes disposing a lower-layer wiring pattern on an imaginary lower-layer wiring layer and an upper-layer wiring pattern perpendicular to the lower-layer wiring pattern on an imaginary upper-layer wiring layer implemented in the graphics image space, providing a detour pattern including a first detour pattern connected to the upper-layer wiring pattern, providing a plurality of via patterns connecting the lower-layer and upper-layer wiring patterns, and forming a via cell pattern.
摘要翻译：半导体集成电路的制造方法使用通过一系列工序设计的布局数据。处理顺序包括在虚拟的下层布线层和在图形图像空间中实现的虚拟上层布线层上垂直于下层布线图案布置下层布线图案，提供包括连接到上层布线图案的第一绕行图案的绕曲图形，提供连接下层布线图案和上层布线图案的多个通孔图案，以及形成通孔单元图案。

53. 发明申请

US20060166434A1 Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit 失效
标题翻译：用于设计半导体集成电路和半导体集成电路的计算机实现方法
公开(公告)号：US20060166434A1
公开(公告)日：2006-07-27
申请号：US11320643
申请日：2005-12-30
申请人： Koichi Kinoshita , Yukihiro Urakawa
发明人： Koichi Kinoshita , Yukihiro Urakawa
IPC分类号： H01L21/8242 , H01L23/48 , H01L23/52
CPC分类号： G06F17/5068 , H01L23/522 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.
摘要翻译：一种用于设计半导体集成电路的计算机实现方法包括：基于第一电力线的放置结果，将伪图案放置在位于第一电力线正上方的第二互连层上，虚设图案具有与第一电力线的方向平行的长轴第一电力线; 并且基于第一电力线和虚拟图案的配置结果，将虚设图案电连接到第一电力线。

54. 发明申请

US20050189607A1 Upper-layer metal power standard cell 失效
标题翻译：上层金属电源标准电池
公开(公告)号：US20050189607A1
公开(公告)日：2005-09-01
申请号：US11060727
申请日：2005-02-18
申请人： Takeshi Yoshida , Yukihiro Urakawa
发明人： Takeshi Yoshida , Yukihiro Urakawa
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/10 , H01L27/118
CPC分类号： H01L27/11807 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An upper-layer metal power standard cell comprises: a basic power metal layer which is disposed in an upper layer of a circuit and which supplies a power voltage from an outside of the upper-layer metal power standard cell; a transistor element layer which is formed in a predetermined arrangement on a circuit substrate under the basic power metal layer; and an inner wire layer which supplies the power voltage to the transistor element layer disposed under the basic power metal layer disposed in the upper layer from the basic power metal layer.
摘要翻译：上层金属电力标准电池包括：基本功率金属层，其设置在电路的上层中，并从上层金属电力标准电池的外部提供电力电压; 在基本功率金属层下的电路基板上以预定的布置形成的晶体管元件层; 以及内部电线层，其将功率电压提供到从基本功率金属层设置在上层中的基本功率金属层下方的晶体管元件层。

55. 发明授权

US06737743B2 Memory chip and semiconductor device using the memory chip and manufacturing method of those 失效
标题翻译：内存芯片和半导体器件采用的是内存芯片及其制造方法
公开(公告)号：US06737743B2
公开(公告)日：2004-05-18
申请号：US10190500
申请日：2002-07-09
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： H01L2334
CPC分类号： H01L25/18 , G11C5/04 , G11C7/1045 , G11C11/005 , G11C29/006 , G11C2029/1804 , H01L22/20 , H01L22/22 , H01L23/544 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L27/10897 , H01L2223/54406 , H01L2223/5446 , H01L2223/54473 , H01L2223/5448 , H01L2224/16145 , H01L2224/32225 , H01L2224/451 , H01L2224/48137 , H01L2224/48227 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2924/00015
摘要： In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A Dicing line is interposed between four basic chips F configuring the memory chip. Four basic chips F can change a word organization by a control signal individually.
摘要翻译：在晶片中，配置有多个基本芯片F. 基本芯片F具有i兆字节的存储容量。通过切割，从晶片上切出包括四个基本芯片F的存储芯片。存储器芯片的存储容量为4xi兆字节。切割线插入配置存储器芯片的四个基本芯片F之间。四个基本芯片F可以通过单独的控制信号改变单词组织。

56. 发明授权

US06462995B2 Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device 有权
标题翻译：能够恢复有缺陷的位的半导体存储器件和具有相同半导体存储器件的系统
公开(公告)号：US06462995B2
公开(公告)日：2002-10-08
申请号：US09975149
申请日：2001-10-12
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： G11C700
CPC分类号： G11C29/812
摘要： The present invention provides a semiconductor memory device capable of simplifying a test process for a memory circuit containing a nonvolatile memory while reducing an overhead of its chip area and a system incorporating the same semiconductor memory device. This semiconductor memory device comprises a proper memory cell array, a redundant memory cell with which the defective memory cell in the proper memory cell array is to be replaced, a register for holding defect information of the defective memory cell detected in the proper memory cell array temporarily; a control circuit for replacing the defective memory cell with the redundant memory cell according to the defect information of the memory cell held in the register, a redundant program array which is an expansion of the same memory cell as the proper memory cell array while sharing a column with the proper memory cell array so as to store defect information in the same column as the defective memory cell, a writing circuit for writing defect information held in the register into the redundant program array, and a reading circuit for reading the defect information stored in the redundant program array into the register.
摘要翻译：本发明提供一种半导体存储器件，其能够简化对包含非易失性存储器的存储电路的测试处理，同时减少其芯片面积的开销以及包含相同的半导体存储器件的系统。该半导体存储器件包括适当的存储单元阵列，用于替换正确的存储单元阵列中的有缺陷的存储单元的冗余存储单元，用于保存在适当的存储单元阵列中检测到的有缺陷的存储单元的缺陷信息的寄存器暂时; 用于根据保存在寄存器中的存储单元的缺陷信息用冗余存储器单元替换缺陷存储单元的控制电路;冗余程序阵列，其是与正确的存储单元阵列相同的存储单元的扩展，同时共享具有适当的存储单元阵列的列，以便将缺陷信息存储在与缺陷存储单元相同的列中;写入电路，用于将保存在寄存器中的缺陷信息写入冗余程序阵列;以及读取电路，用于读取存储的缺陷信息在冗余程序阵列中进入寄存器。

57. 发明授权

US06324106B2 Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device 有权
标题翻译：能够恢复有缺陷的位的半导体存储器件和具有相同半导体存储器件的系统
公开(公告)号：US06324106B2
公开(公告)日：2001-11-27
申请号：US09860911
申请日：2001-05-21
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： G11C700
CPC分类号： G11C29/812
摘要： The present invention provides a semiconductor memory device capable of simplifying a test process for a memory circuit containing a nonvolatile memory while reducing an overhead of its chip area and a system incorporating the same semiconductor memory device. This semiconductor memory device comprises a proper memory cell array, a redundant memory cell with which the defective memory cell in the proper memory cell array is to be replaced, a register for holding defect information of the defective memory cell detected in the proper memory cell array temporarily; a control circuit for replacing the defective memory cell with the redundant memory cell according to the defect information of the memory cell held in the register, a redundant program array which is an expansion of the same memory cell as the proper memory cell array while sharing a column with the proper memory cell array so as to store defect information in the same column as the defective memory cell, a writing circuit for writing defect information held in the register into the redundant program array, and a reading circuit for reading the defect information stored in the redundant program array into the register.
摘要翻译：本发明提供一种半导体存储器件，其能够简化对包含非易失性存储器的存储电路的测试处理，同时减少其芯片面积的开销以及包含相同的半导体存储器件的系统。该半导体存储器件包括适当的存储单元阵列，用于替换正确的存储单元阵列中的有缺陷的存储单元的冗余存储单元，用于保存在适当的存储单元阵列中检测到的有缺陷的存储单元的缺陷信息的寄存器暂时; 用于根据保存在寄存器中的存储单元的缺陷信息用冗余存储器单元替换缺陷存储单元的控制电路;冗余程序阵列，其是与正确的存储单元阵列相同的存储单元的扩展，同时共享具有适当的存储单元阵列的列，以便将缺陷信息存储在与缺陷存储单元相同的列中;写入电路，用于将保存在寄存器中的缺陷信息写入冗余程序阵列;以及读取电路，用于读取存储的缺陷信息在冗余程序阵列中进入寄存器。

58. 发明授权

US06246617B1 Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device 有权
公开(公告)号：US06246617B1
公开(公告)日：2001-06-12
申请号：US09523177
申请日：2000-03-10
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： G11C700
CPC分类号： G11C29/812
摘要： The present invention provides a semiconductor memory device capable of simplifying a test process for a memory circuit containing a nonvolatile memory while reducing an overhead of its chip area and a system incorporating the same semiconductor memory device. This semiconductor memory device comprises a proper memory cell array, a redundant memory cell with which the defective memory cell in the proper memory cell array is to be replaced, a register for holding defect information of the defective memory cell detected in the proper memory cell array temporarily; a control circuit for replacing the defective memory cell with the redundant memory cell according to the defect information of the memory cell held in the register, a redundant program array which is an expansion of the same memory cell as the proper memory cell array while sharing a column with the proper memory cell array so as to store defect information in the same column as the defective memory cell, a writing circuit for writing defect information held in the register into the redundant program array, and a reading circuit for reading the defect information stored in the redundant program array into the register.

59. 发明授权

US5991230A Synchronous random access memory 失效
标题翻译：同步随机存取存储器
公开(公告)号：US5991230A
公开(公告)日：1999-11-23
申请号：US44093
申请日：1998-03-19
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/41 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a synchronous random access memory, a data readout period, a data writein period, and a precharge period (or a reset period) are performed in order under the control of a control circuit 10, and the synchronous random access memory operates so that the executions of the data readout operation and the data writein operation are not overlapped under the control of the control circuit 10 comprising a sense amplifier activation generation circuit 11, a writein control signal generation circuit 12, and a reset signal generation circuit 13.
摘要翻译：在同步随机存取存储器中，在控制电路10的控制下依次执行数据读出期间，数据写入期间和预充电期间（或复位期间），同步随机存取存储器的动作使得在包括读出放大器激活生成电路11，写入控制信号生成电路12和复位信号生成电路13的控制电路10的控制下，数据读出操作和数据写入操作的执行不重叠。

60. 发明授权

US5399894A Semiconductor device having bipolar transistor and MOS transistor 失效
标题翻译：具有双极晶体管和MOS晶体管的半导体器件
公开(公告)号：US5399894A
公开(公告)日：1995-03-21
申请号：US23153
申请日：1992-10-28
申请人： Takeo Maeda , Hiroshi Momose , Yukihiro Urakawa , Masataka Matsui
发明人： Takeo Maeda , Hiroshi Momose , Yukihiro Urakawa , Masataka Matsui
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/165 , H01L29/737 , H01L27/02 , H01L29/161
CPC分类号： H01L27/0623 , H01L29/7378
摘要： A semiconductor device of the present invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is heterojunction transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.
摘要翻译：本发明的半导体器件包括形成在同一半导体衬底上的双极晶体管和MOS晶体管。双极晶体管是具有异质结的异质结晶体管。异双极晶体管是双异质结构的双极晶体管，其中用于形成其基极区的材料的带隙比用于形成其发射极和集电极区域的材料窄。

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