会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 52. 发明授权
    • Error-suppressing phase comparator
    • 误差抑制相位比较器
    • US06249188B1
    • 2001-06-19
    • US09528998
    • 2000-03-20
    • Yoshiaki Kaneko
    • Yoshiaki Kaneko
    • H03L7085
    • H03L7/095H03D13/004H03L7/089H04L7/033Y10S331/02
    • Provided are a phase comparator (BBD) 10 for generating a pulse of a signal UP0 or DOWN0 depending on lead or lag of the falling edge of a clock recovered from DATA, relative to the edge of DATA, an overrun detector circuit 20 activating an overrun signal OVR while the circuit 20 detects that lead or lag of the falling edge of the clock exceeds &pgr;/2, a state latch circuit 30 latching a state of either a signal UP0 or DOWN0 being active before the signal OVR transits active, and a selection circuit 40 outputting the signals UP0 and DOWN0 as signals UP and DOWN while the signal OVR is inactive, and outputting the signals UP0 and DOWN0 as the signals DOWN and UP while the signal OVR is active.
    • 提供了一种相位比较器(BBD)10,用于相对于DATA的边缘,根据从DATA恢复的时钟的下降沿的引导或滞后来产生信号UP0或DOWN0的脉冲,超限检测器电路20激活超限 信号OVR,而电路20检​​测到时钟的下降沿的引导或延迟超过pi / 2,在信号OVR转换为有效之前锁存信号UP0或DOWN0的状态的状态锁存电路30处于活动状态,以及选择 电路40在信号OVR无效时输出信号UP0和DOWN0作为信号UP和DOWN,并且在信号OVR有效时将信号UP0和DOWN0作为信号DOWN和UP输出。