专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US5217915A Method of making gate array base cell 失效
标题翻译：制造栅极阵列基体的方法
公开(公告)号：US5217915A
公开(公告)日：1993-06-08
申请号：US681822
申请日：1991-04-08
申请人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
发明人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/118
CPC分类号： H01L27/11807 , H01L21/8238
摘要： A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

52. 发明授权

US5068825A Memory cell circuit and operation thereof 失效
标题翻译：存储单元电路及其操作
公开(公告)号：US5068825A
公开(公告)日：1991-11-26
申请号：US546497
申请日：1990-06-29
申请人： Shivaling S. Mahant-Shetti , Mark G. Harward
发明人： Shivaling S. Mahant-Shetti , Mark G. Harward
IPC分类号： G11C11/413 , G11C11/412 , G11C11/418
CPC分类号： G11C11/412
摘要： An improved memory cell 118 is provided utilizing transistor pairs 142, 144 ands 160, 162 as dual purpose transistor pairs for the two modes of operation of the cell. During the first or non-access mode of operation, the transistor pairs operate as switched capacitive elements in order to provide an equivalent resistance between bit line 140 and first node 26 and inverted bit line 158 and second node 130. Control circuit 119 maintains bit lines 140 and inverted bit line 158 high during this non-access mode. During the second or access mode of operation, each transistor pair operates as a respective pass transistor for connecting bit line 140 to first node 126 and inverted bit line 158 to second node 130 so that data may be read from, or written to, the cross-coupled transistors 120 and 122.

53. 发明授权

US4601019A Memory with redundancy 失效
标题翻译：内存冗余
公开(公告)号：US4601019A
公开(公告)日：1986-07-15
申请号：US528209
申请日：1983-08-31
申请人： Ashwin H. Shah , James D. Gallia , I-Fay Wang , Shivaling S. Mahant-Shetti
发明人： Ashwin H. Shah , James D. Gallia , I-Fay Wang , Shivaling S. Mahant-Shetti
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/808
摘要： A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received column address and the stored defective-column-address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever word line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has even been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.
摘要翻译：具有列冗余的字节宽的内存。冗余列可以分别代替半数组中的任何列，而不考虑缺陷列与哪个位的关系。保险丝存储有缺陷列的地址信息，当外部接收的列地址与存储的故障列地址之间的匹配被找到时，包含该缺陷列的位位置的读出放大器被禁止，并且输出冗余列（由哪个字线被激活选择）被复用到IO总线中。因此，在行地址信号甚至被解码之前，有缺陷的列已经被禁用，并且冗余列之一被有效地替代。该配置意味着对于每个位位置不需要具有一个冗余列，但是每个冗余列可以替代任何位位置中的有缺陷的列，并且可以替换单个位位置中的多于一个的有缺陷的列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式