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51. 发明申请

US20080074826A1 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US20080074826A1
公开(公告)日：2008-03-27
申请号：US11902398
申请日：2007-09-21
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/30
CPC分类号： H01G4/232 , H01G4/30
摘要： A multilayer chip capacitor including: a capacitor body where a plurality of dielectric layers are deposited, the capacitor body having opposing first and second sides and opposing third and fourth sides; a plurality of layers of internal electrodes deposited alternately with the dielectric layers in the capacitor body; at least one first external electrode formed on the first side; and at least one second external electrode formed on the second side, wherein the first and second external electrodes are staggered with respect to each other and spaced apart from each other at a certain distance in a length direction of the first side.
摘要翻译：一种多层片状电容器，包括：电容器体，其中沉积有多个电介质层，所述电容器体具有相对的第一和第二侧以及相对的第三和第四侧; 与电容器主体中的电介质层交替沉积的多层内部电极; 形成在所述第一侧上的至少一个第一外部电极; 以及形成在所述第二侧上的至少一个第二外部电极，其中所述第一和第二外部电极相对于彼此交错并且在所述第一侧的长度方向上以一定距离彼此间隔开。

52. 发明授权

US07292430B2 Multi-layer chip capacitor 失效
标题翻译：多层片式电容器
公开(公告)号：US07292430B2
公开(公告)日：2007-11-06
申请号：US11272877
申请日：2005-11-15
申请人： Byoung Hwa Lee , Chang Hoon Shim , Kyong Nam Hwang , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Chang Hoon Shim , Kyong Nam Hwang , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/30
摘要： A multi-layer chip capacitor includes a capacitor body; first and second internal electrodes alternately arranged therein and separated by dielectric layers, each of the internal electrodes having at least one opening formed at one or more sides thereof; first and second conductive vias passing through the openings and electrically connected to the first and second internal electrodes, respectively; first and second terminal electrodes of opposite polarities formed on one or more side faces of the capacitor body; and first and second lowermost electrode patterns being coplanar, each pattern including a via contact portion and a lead portion extending therefrom. The first and second lowermost electrode patterns are connected to the first and second terminal electrodes, respectively, through the respective lead portions of the lowermost patterns.
摘要翻译：多层片式电容器包括电容器体; 第一和第二内部电极交替地布置在其中并由电介质层分离，每个内部电极具有形成在其一侧或多侧的至少一个开口; 第一和第二导电通孔分别穿过开口并电连接到第一和第二内部电极; 形成在电容器主体的一个或多个侧面上的相反极性的第一和第二端子电极; 并且第一和第二最低电极图案是共面的，每个图案包括通孔接触部分和从其延伸的引线部分。第一和第二最下面的电极图案分别通过最下面图案的相应引线部分连接到第一和第二端子电极。

53. 发明授权

US07236064B2 Laminated balun transformer 有权
标题翻译：叠层平衡不平衡变压器
公开(公告)号：US07236064B2
公开(公告)日：2007-06-26
申请号：US11067872
申请日：2005-02-28
申请人： Byoung Hwa Lee , Dong Seok Park , Min Cheol Park , Sang Soo Park
发明人： Byoung Hwa Lee , Dong Seok Park , Min Cheol Park , Sang Soo Park
IPC分类号： H03H7/42 , H01P5/10
CPC分类号： H01P5/10
摘要： The present invention relates a laminated balun transformer with an improved insertion loss characteristic in a pass band. The laminated balun transformer includes a first strip line and a third strip line form one coupler, a second strip line and a fourth strip line form another coupler, and a conductive non-ground electrode formed at an intermediate position between the third strip line and the fourth strip line. The non-ground electrode forms a ground by electromagnetic coupling between the third strip line and the fourth strip line. With the configuration, insertion loss in an operation band is reduced. In addition, by implementing an impedance and an electromagnetic shield using a ground pattern of a mount surface without separately forming an internal ground electrode on the bottom layer of a dielectric block, of ground electrodes formed above and below the first to fourth strip lines for the electromagnetic shield from the outside, the thickness of the laminated balun transformer can be reduced without any deterioration of characteristic of the transformer.
摘要翻译：本发明涉及在通带中具有改进的插入损耗特性的层叠平衡不平衡变压器。所述叠层平衡不平衡转换器包括形成一个耦合器的第一带状线和第三带状线，形成另一个耦合器的第二带状线和第四带状线，以及形成在第三带状线和第三带状线之间的中间位置的导电非接地电极第四条线。非接地电极通过第三带状线和第四带状线之间的电磁耦合形成接地。通过该结构，能够减少操作频带的插入损失。此外，通过使用安装面的接地图案来实现阻抗和电磁屏蔽，而不在介质块的底层上分开形成内部接地电极，形成在第一至第四条带状线之上和之下的接地电极，用于电磁屏蔽从外部，层压平衡不平衡变压器的厚度可以减小，而不会导致变压器特性的恶化。

54. 发明申请

US20070123014A1 Method for fabricating semiconductor device having flask type recess gate 有权
标题翻译：具有烧瓶式凹槽的半导体器件的制造方法
公开(公告)号：US20070123014A1
公开(公告)日：2007-05-31
申请号：US11496428
申请日：2006-08-01
申请人： Ky-Hyun Han , Sang-Soo Park
发明人： Ky-Hyun Han , Sang-Soo Park
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4236 , H01L29/66621
摘要： A method for fabricating a semiconductor device having a flask type recess gate includes forming a hard mask pattern on a substrate, etching the substrate to a predetermined depth using the hard mask pattern to form a first recess pattern, forming a passivation layer on sidewalls of the first recess pattern and the hard mask pattern, etching a bottom surface of the first recess pattern exposed by the passivation layer to form a second recess pattern, oxidizing sidewalls of the second recess pattern to form a silicon oxide layer, removing the passivation layer and the silicon oxide layer in sequential order, and forming a gate pattern over an intended recess pattern including the first recess pattern and the second recess pattern.
摘要翻译：一种用于制造具有烧瓶式凹槽的半导体器件的方法，包括在衬底上形成硬掩模图案，使用硬掩模图案将衬底蚀刻到预定深度以形成第一凹陷图案，在第二凹陷图案的侧壁上形成钝化层蚀刻由钝化层暴露的第一凹陷图案的底表面以形成第二凹槽图案，氧化第二凹槽图案的侧壁以形成氧化硅层，去除钝化层和钝化层，氧化硅层，并且在包括第一凹槽图案和第二凹陷图案的预期凹槽图案上形成栅极图案。

55. 发明授权

US07035079B1 Multilayered chip capacitor and multilayer chip capacitor array 失效
标题翻译：多层片式电容器和多层片式电容阵列
公开(公告)号：US07035079B1
公开(公告)日：2006-04-25
申请号：US11247404
申请日：2005-10-11
申请人： Sang Soo Park , Dong Seok Park , Byoung Hwa Lee , Min Cheol Park , Hyun Ju Yi , Min Kyoung Kwon , Hae Suk Chung , Chang Hoon Shim , Seung Heon Han
发明人： Sang Soo Park , Dong Seok Park , Byoung Hwa Lee , Min Cheol Park , Hyun Ju Yi , Min Kyoung Kwon , Hae Suk Chung , Chang Hoon Shim , Seung Heon Han
IPC分类号： H01G4/005 , H01G4/236 , H01G4/20
CPC分类号： H01G4/232 , H01G4/012
摘要： The present invention provides an MLCC and an MLCC array. The MLCC has desirably low ESL properties by forming the first and second internal electrodes to be spaced apart from each other on the same dielectric layer while overlapping with other first and second internal electrodes on the neighboring dielectric layers, and connecting the first and second internal electrodes to the external terminals provided on the top surface or the bottom surface of the capacitor body through conductive via holes formed in the capacitor body in a stacking direction of the capacitor body.
摘要翻译：本发明提供了MLCC和MLCC阵列。通过在相同的电介质层上形成第一和第二内部电极彼此间隔开，同时与相邻电介质层上的其它第一和第二内部电极重叠，并且连接第一和第二内部电极通过形成在电容器主体中的电容器本体的堆叠方向上的导电通孔，连接到设置在电容器主体的顶表面或底表面上的外部端子。

56. 发明授权

US06465356B2 Method for forming fine patterns by thinning developed photoresist patterns using oxygen radicals 有权
公开(公告)号：US06465356B2
公开(公告)日：2002-10-15
申请号：US09894155
申请日：2001-06-27
申请人： Gi-Hyeon Kim , Sang-Soo Park
发明人： Gi-Hyeon Kim , Sang-Soo Park
IPC分类号： H01L21311
CPC分类号： H01L21/31138 , G03F7/40
摘要： The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a photoresist pattern to form a fine line width of about 0.1 &mgr;m or less. A method for forming fine photoresist patterns according to the present invention comprises the step of: forming photoresist patterns over a semiconductor substrate using a stepper; and ashing the photoresist patterns using oxygen radicals in order to decrease line width of the photoresist patterns. The oxygen radicals are formed by a thermal decomposition of an ozone gas in an ozone asher. Accordingly, the present invention overcomes the resolution of the stepper by controlling the ashing rate at a low temperature using the oxygen radicals in the ozone asher.

57. 发明申请

US20170125128A1 NONVOLATILE MEMORY DEVICE AND A METHOD OF OPERATING THE SAME 有权
公开(公告)号：US20170125128A1
公开(公告)日：2017-05-04
申请号：US15207774
申请日：2016-07-12
申请人： JI-SANG LEE , SANG-SOO PARK , DONG-KYO SHIM
发明人： JI-SANG LEE , SANG-SOO PARK , DONG-KYO SHIM
IPC分类号： G11C29/56 , G11C8/10 , G11C7/12 , G11C7/14 , G11C7/22 , G11C7/10
CPC分类号： G11C29/1201 , G11C7/1006 , G11C7/1039 , G11C7/1057 , G11C7/106 , G11C7/12 , G11C7/14 , G11C7/222 , G11C8/10 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C27/02 , G11C29/42 , G11C29/50012 , G11C29/52 , G11C29/56008 , G11C2029/0411 , G11C2029/5004 , G11C2211/5642
摘要： A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K≦N, L>1, P≦M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.

58. 发明申请

US20170123724A1 MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
公开(公告)号：US20170123724A1
公开(公告)日：2017-05-04
申请号：US15336014
申请日：2016-10-27
申请人： SANG-SOO PARK , DONG-KYO SHIM
发明人： SANG-SOO PARK , DONG-KYO SHIM
IPC分类号： G06F3/06 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/34 , G11C16/16
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/0685 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3459 , G11C2211/5642 , G11C2211/5643 , G11C2211/5644
摘要： A memory device is provided as follows. A memory cell array includes a plurality of memory cells, and the plurality of memory cells are divided into a first memory group and a second memory group. A first page buffer group is coupled to the first memory group and includes a plurality of first page buffers. A second page buffer group is coupled to the second memory group and includes a plurality of second page buffers. The first page buffer group performs a first data processing operation on data stored in the first page buffer group and stores a result of the first data processing operation. The second page buffer group performs a second data processing operation on data stored in the second page buffer group and stores a result of the second data processing operation. The first and second data processing operations are performed at substantially the same.

59. 发明授权

US09099242B2 Laminated chip electronic component, board for mounting the same, and packing unit thereof 有权
标题翻译：层叠芯片电子部件，用于安装其的基板及其包装单元
公开(公告)号：US09099242B2
公开(公告)日：2015-08-04
申请号：US13588696
申请日：2012-08-17
申请人： Young Ghyu Ahn , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
发明人： Young Ghyu Ahn , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
IPC分类号： H05K1/16 , H01G4/005 , H05K1/02 , H01G4/30
CPC分类号： H01G4/005 , H01G4/30 , H05K1/0271 , H05K1/111 , H05K3/3442 , H05K2201/09427 , H05K2201/10015 , H05K2201/10636 , H05K2201/2045 , Y02P70/611
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.
摘要翻译：层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。

60. 发明授权

US08638543B2 Laminated chip electronic component, board for mounting the same, and packing unit thereof 有权
标题翻译：层叠芯片电子部件，用于安装其的基板及其包装单元
公开(公告)号：US08638543B2
公开(公告)日：2014-01-28
申请号：US13588876
申请日：2012-08-17
申请人： Young Ghyu Ahn , Min Cheol Park , Doo Young Kim , Sang Soo Park
发明人： Young Ghyu Ahn , Min Cheol Park , Doo Young Kim , Sang Soo Park
IPC分类号： H01G4/06 , H01G4/005
CPC分类号： H01G4/30 , B65B9/04 , B65B15/04 , H01G2/065 , H01G4/012 , H01G4/12 , H05K1/181 , H05K2201/10015
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.
摘要翻译：层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的第一外部电极和第二外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 上下层形成在有源层的厚度方向的上部和下部上，下覆盖层的厚度大于上覆盖层的厚度; 以及与下覆盖层内的电容的形成无关地设置的附加电极层。

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