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51. 发明授权

US07154788B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07154788B2
公开(公告)日：2006-12-26
申请号：US10995198
申请日：2004-11-24
申请人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
IPC分类号： G11C11/34
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

52. 发明授权

US07057243B2 Hybrid semiconductor device having an n+ (p) doped n-type gate and method of producing the same 有权
标题翻译：具有n +（p）掺杂n型栅极的混合半导体器件及其制造方法
公开(公告)号：US07057243B2
公开(公告)日：2006-06-06
申请号：US10648883
申请日：2003-08-27
申请人： Satoru Yamada , Ryo Nagai , Kiyonori Oyu , Ryoichi Nakamura , Norikatsu Takaura
发明人： Satoru Yamada , Ryo Nagai , Kiyonori Oyu , Ryoichi Nakamura , Norikatsu Takaura
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L21/28061 , H01L21/823842 , H01L27/10894 , H01L27/10897 , H01L29/4941 , H01L29/7833
摘要： In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.
摘要翻译：在具有三个或更多个不同费米能级的多晶硅栅电极结构的半导体器件中，具有最低费米能级的P型多晶硅设置在第一N型表面沟道MOS晶体管上。具有最高费米能级的第一N型多晶硅被布置在第二N型表面沟道MOS晶体管上。具有最高和最低费米能级之间的中间费米能级并且掺杂有N型杂质和P型杂质的第二N型多晶硅设置在P沟道MOS晶体管上。

53. 发明申请

US20050128799A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050128799A1
公开(公告)日：2005-06-16
申请号：US11002245
申请日：2004-12-03
申请人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka
发明人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka
IPC分类号： G11C13/00 , G11C11/00 , G11C13/02 , G11C16/02 , G11C17/00 , H01L27/10
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. At this time, if a constant voltage source is used, not only the phase change portion assumes a state of a low resistance, but also a large current flows, so that a sample concerned is overheated and goes into a state of a high resistance. Thus, it is difficult to make the phase change portion low in resistance stably. When the gate voltage of a memory cell selection transistor QM is controlled with MISFET to afford a low resistance state, the maximum amount of current applied to the sample is limited by the application of a medium-state voltage.
摘要翻译：在非易失性相变存储器中，利用相变部分的电阻变化来记录信息。当相变部分产生焦耳热并保持在特定温度时，其进入低电阻状态。此时，如果使用恒定电压源，则不仅相变部分呈现低电阻状态，而且流过大电流，使得有关样品过热并进入高电阻状态。因此，难以稳定地使相位变化部的电阻低。当用MISFET控制存储单元选择晶体管QM的栅极电压以提供低电阻状态时，施加到样品的最大电流量受到施加中等电压的限制。

54. 发明授权

US08859344B2 Semiconductor memory 有权
公开(公告)号：US08859344B2
公开(公告)日：2014-10-14
申请号：US13314154
申请日：2011-12-07
申请人： Yuichi Matsui , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
发明人： Yuichi Matsui , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
IPC分类号： H01L21/82 , H01L45/00 , H01L27/24
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

55. 发明授权

US08513640B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08513640B2
公开(公告)日：2013-08-20
申请号：US12094403
申请日：2006-11-14
申请人： Takahiro Morikawa , Motoyasu Terao , Norikatsu Takaura , Kenzo Kurotsuchi
发明人： Takahiro Morikawa , Motoyasu Terao , Norikatsu Takaura , Kenzo Kurotsuchi
IPC分类号： H01L29/06 , H01L21/00
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.
摘要翻译：在相同的半导体衬底1上，存储单元阵列，其中具有存储具有高电阻值的高电阻状态的硫族化物材料存储层22的多个存储元件R和具有低电阻的低电阻状态在存储单元区域mmry中形成以矩阵形式设置的原子排列变化的值，在逻辑电路区域lgc中形成半导体集成电路。该硫属化物材料储存层22由含有10.5原子％以上至40原子％以下的Ga或In中的至少任一种的硫属元素化物构成，5原子％以上且35原子％以下的Ge，Sb 为5原子％以上且25原子％以下，Te为40原子％以上且65原子％以下。

56. 发明申请

US20120132879A1 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120132879A1
公开(公告)日：2012-05-31
申请号：US13366544
申请日：2012-02-06
申请人： MASAHARU KINOSHITA , Yoshitaka Sasago , Norikatsu Takaura
发明人： MASAHARU KINOSHITA , Yoshitaka Sasago , Norikatsu Takaura
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/1675 , Y10S438/90
摘要： Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.
摘要翻译：本发明提供一种非易失性存储装置，其包括：配置有交叉点存储单元的相变存储器，其中由相变材料形成的存储元件和由二极管形成的选择元件组合。存储单元配置有由相变材料形成的存储元件和由具有第一多晶硅膜，第二多晶硅膜和第三多晶硅膜的堆叠结构的二极管形成的选择元件。存储单元布置在沿着第一方向延伸的多个第一金属布线的交点和沿着与第一方向正交的第二方向延伸的多个第三金属布线。在相邻的选择元件之间和相邻的存储元件之间形成中间膜，并且在设置在相邻的存储元件之间的层间膜中形成空隙。

57. 发明申请

US20120077325A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20120077325A1
公开(公告)日：2012-03-29
申请号：US13314154
申请日：2011-12-07
申请人： YUICHI MATSUI , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
发明人： YUICHI MATSUI , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
摘要翻译：由于这种材料对高熔点金属和氧化硅膜具有低粘附性，所以相变存储器的制造过程已经受到硫属化物材料易于分层的问题的困扰。此外，硫族化物材料具有低的热稳定性，因此在相变存储器的制造过程中倾向于升华。根据本发明，在硫族化物材料层上和下方形成导电或绝缘粘合剂层以增强其分层强度。此外，在硫族化物材料层的侧壁上形成由氮化物膜构成的保护膜，以防止硫属化物材料层的升华。

58. 发明申请

US20120074377A1 SEMICONDUCTOR MEMORY 有权
公开(公告)号：US20120074377A1
公开(公告)日：2012-03-29
申请号：US13314165
申请日：2011-12-07
申请人： YUICHI MATSUI , Nozomu MATSUZAKI , Norikatsu TAKAURA , Naoki YAMAMOTO , Hideyuki MATSUOKA , Tomio IWASAKI
发明人： YUICHI MATSUI , Nozomu MATSUZAKI , Norikatsu TAKAURA , Naoki YAMAMOTO , Hideyuki MATSUOKA , Tomio IWASAKI
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

59. 发明授权

US08129705B2 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08129705B2
公开(公告)日：2012-03-06
申请号：US12434633
申请日：2009-05-02
申请人： Masaharu Kinoshita , Yoshitaka Sasago , Norikatsu Takaura
发明人： Masaharu Kinoshita , Yoshitaka Sasago , Norikatsu Takaura
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/1675 , Y10S438/90
摘要： Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.
摘要翻译：本发明提供一种非易失性存储装置，其包括：配置有交叉点存储单元的相变存储器，其中由相变材料形成的存储元件和由二极管形成的选择元件组合。存储单元配置有由相变材料形成的存储元件和由具有第一多晶硅膜，第二多晶硅膜和第三多晶硅膜的堆叠结构的二极管形成的选择元件。存储单元布置在沿着第一方向延伸的多个第一金属布线的交点和沿着与第一方向正交的第二方向延伸的多个第三金属布线。在相邻的选择元件之间和相邻的存储元件之间形成中间膜，并且在设置在相邻的存储元件之间的层间膜中形成空隙。

60. 发明申请

US20110283039A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110283039A1
公开(公告)日：2011-11-17
申请号：US13191442
申请日：2011-07-26
申请人： MOTOYASU TERAO , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
发明人： MOTOYASU TERAO , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号： G06F12/06
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C29/50008 , G11C2013/0054 , G11C2213/72
摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
摘要翻译：为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

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