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51. 发明授权

US06878639B1 Borderless interconnection process 有权
标题翻译：无边界互连过程
公开(公告)号：US06878639B1
公开(公告)日：2005-04-12
申请号：US10667013
申请日：2003-09-19
申请人： Ming-Huan Tsai , Ru-Chian Chiang , Hun-Jan Tao
发明人： Ming-Huan Tsai , Ru-Chian Chiang , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L21/311 , H01L21/60
CPC分类号： H01L21/76897 , H01L21/31105 , H01L21/31116
摘要： A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.
摘要翻译：提供了一种在半导体器件中制造无边界互连的新方法。在制造期间，器件包括层间电介质（ILD）层，金属硅化物层和设置在ILD和金属硅化物层之间的阻挡层。阻挡层可以由氮化硅或氮氧化硅形成，并且金属硅化物层可以是硅化镍。该方法包括蚀刻ILD层以暴露停止层的至少一部分，然后在停止层的暴露部分上进行氮等离子体处理。在处理之后，去除停止层的暴露部分以提供互连孔。由于等离子体处理，当停止层被去除时，对停止层下面的金属硅化物的损坏将被最小化。

52. 发明授权

US06787455B2 Bi-layer photoresist method for forming high resolution semiconductor features 失效
标题翻译：用于形成高分辨率半导体特征的双层光致抗蚀剂方法
公开(公告)号：US06787455B2
公开(公告)日：2004-09-07
申请号：US10032353
申请日：2001-12-21
申请人： Ming-Huan Tsai , Hun-Jan Tao , Ju-Wang Hsu , Cheng-Ku Chen
发明人： Ming-Huan Tsai , Hun-Jan Tao , Ju-Wang Hsu , Cheng-Ku Chen
IPC分类号： H01L214763
CPC分类号： G03F7/094 , H01L21/0274 , H01L21/76802
摘要： A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist over the non-silicon containing photoresist layer; exposing said silicon containing photoresist layer to an activating light source an exposure surface defined by an overlying pattern according to a photolithographic process; developing said silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least oxygen, carbon monoxide, and argon.
摘要翻译：一种使用双层光致抗蚀剂的半导体器件特征显影的方法，包括在衬底上提供不含硅的光致抗蚀剂层; 在含硅光致抗蚀剂层上提供含硅光致抗蚀剂; 将所述含硅光致抗蚀剂层暴露于激活光源，根据光刻工艺由覆盖图案限定的曝光表面; 根据光刻工艺显影所述含硅光致抗蚀剂层以露出含有非硅的光致抗蚀剂层的一部分; 以及通过从包括至少氧，一氧化碳和氩的环境混合物点燃等离子体，在等离子体反应器中干燥显影所述不含硅的光致抗蚀剂层。

53. 发明授权

US06720132B2 Bi-layer photoresist dry development and reactive ion etch method 失效
标题翻译：双层光致抗蚀剂干式显影和反应离子蚀刻方法
公开(公告)号：US06720132B2
公开(公告)日：2004-04-13
申请号：US10043015
申请日：2002-01-08
申请人： Ming Huan Tsai , Hun-Jan Tao
发明人： Ming Huan Tsai , Hun-Jan Tao
IPC分类号： G03F736
CPC分类号： G03F7/265 , G03F7/075 , G03F7/094 , G03F7/36
摘要： A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure surface of the silicon containing photoresist layer to an activating light source said exposure surface defined by an overlying pattern according to a photolithographic process; developing the silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least hydrogen and carbon monoxide.
摘要翻译：一种使用双层光致抗蚀剂的半导体器件特征显影的方法，包括在衬底上提供不含硅的光致抗蚀剂层; 在含硅光致抗蚀剂层之上提供含硅光致抗蚀剂层; 将含硅光致抗蚀剂层的曝光表面暴露于根据光刻工艺由覆盖图案限定的所述曝光表面的激活光源; 根据光刻工艺显影含硅光致抗蚀剂层以露出不含硅光致抗蚀剂层的部分; 以及通过从包括至少氢和一氧化碳的环境混合物点燃等离子体，在等离子体反应器中干燥显影所述不含硅的光致抗蚀剂层。

54. 发明授权

US06399437B1 Enhanced side-wall stacked capacitor 失效
标题翻译：增强侧壁堆叠电容器
公开(公告)号：US06399437B1
公开(公告)日：2002-06-04
申请号：US09099258
申请日：1998-06-18
申请人： Yung-Yi Hsu , Yi-Tsai Yi , Chia-Shun Hsiao , Ming-Huan Tsai
发明人： Yung-Yi Hsu , Yi-Tsai Yi , Chia-Shun Hsiao , Ming-Huan Tsai
IPC分类号： H01L218242
CPC分类号： H01L28/87 , H01L28/91
摘要： A method of forming a stacked capacitor having improved capacitance in a dynamic random access memory device is provided wherein and additional pad polysilicon layer is deposited prior to the forming of the capacitor cell contact area such that the side-wall of the capacitor cell can be increased. The increased side-wall thickness of the capacitor cell leads to an improved capacitance value for the cell. The present invention also provides a stacked capacitor formed in a semiconductor device that contains an additional pad polysilicon layer for increasing the thickness of the capacitor side-wall and subsequently its capacitance.
摘要翻译：提供了一种在动态随机存取存储器件中形成具有改善的电容的叠层电容器的方法，其中在形成电容器单元接触区域之前淀积另外的焊盘多晶硅层，使得电容器单元的侧壁可以增加。电容器单元的增加的侧壁厚度导致电池的电容值改善。本发明还提供一种形成在半导体器件中的堆叠电容器，其包含用于增加电容器侧壁的厚度和随后的电容的附加焊盘多晶硅层。

55. 发明授权

US06251791B1 Eliminating etching microloading effect by in situ deposition and etching 有权
标题翻译：通过原位沉积和蚀刻消除蚀刻微载荷效应
公开(公告)号：US06251791B1
公开(公告)日：2001-06-26
申请号：US09357246
申请日：1999-07-20
申请人： Ming-Huan Tsai , Chan-Lon Yang
发明人： Ming-Huan Tsai , Chan-Lon Yang
IPC分类号： H01L21311
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method for eliminating the etching microloading effect is proposed for the invention. Spirit of the invention is that a coating layer is formed on a photo-resist that covers a substrate before the substrate is etched, where coating layer maybe a polymer layer or a dielectric layer. Because step coverage of the coating layer is limited by the aspect of trench, for photo-resist it means the width of openings, it is indisputable that depth of coating layer on bottom of a narrow opening is smaller than depth of coating layer on bottom of a wide opening. Therefore, during following etching process, although etching microloading effect induces etching rate is higher in the wide opening and is lower in the narrow opening, but the thicker coating layer on bottom of the wide opening also requires larger etching time than the narrow opening. Consequently, it is crystal-clear that the etching microloading effect is cancelled and then depth of the wide trench is equal to depth of the narrow trench.
摘要翻译：本发明提出了一种消除蚀刻微加载效应的方法。本发明的精神是在蚀刻基板之前在覆盖基板的光致抗蚀剂上形成涂层，其中涂层可以是聚合物层或电介质层。由于涂层的层间覆盖受到沟槽的限制，对于光刻胶而言，它意味着开口的宽度，不可否认，窄开口底部的涂层深度小于底部的涂层深度一个广阔的开幕因此，在随后的蚀刻过程中，虽然蚀刻微加载效应导致在宽开口中的蚀刻速率较高，而在窄开口中蚀刻速率较低，但是宽开口底部较厚的涂层也需要比窄开口更大的蚀刻时间。因此，清楚的是蚀刻微加载效应被消除，然后宽沟槽的深度等于窄沟槽的深度。

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