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51. 发明专利

JPH08264730A BURIED MEMORY CELL AND BURIED WORD LINE DRIVER IN ASIC PROCESS FOR DRAM 失效
公开(公告)号：JPH08264730A
公开(公告)日：1996-10-11
申请号：JP32439195
申请日：1995-12-13
申请人： MOSAID TECHNOLOGIES INC
发明人： KAARU SUKUJIYAIBURANDO , PIITAA BII GIRINGAMU
IPC分类号： H01L27/108 , G11C8/08 , G11C11/404 , G11C11/407 , G11C11/408 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To unnecessitate the supply of backside bias voltage which was required in the past by a method wherein high positive voltage is used for biasing of well region and for formation of the channel inverted region of a capacitor field effect device, and the gate of the capacitor and an FET are connected. SOLUTION: A P-channel FET and a capacitor are arranged leaving an interval from the cell access of the capacitor contained in the N-well of a P-substrate 8. Besides, a P-doped region 19 is contained in the N-well in the vicinity of the edge of a plate 11, and it is connected to high positive voltage Vpp . As a result, a P-channel is formed under the plate 11. An N-doped region 21 is arranged leaving an interval from the P-doped region 10, it is connected to the Vpp and an N-well 14 is applied. The source and the drain of the capacitor are connected to the Vpp , and also they are connected to the drain of an FET 1. The plate 11 is connected to the drain of the FET 1 and backside bias VBB is not used.

52. 发明专利

JPH08106786A FLIP-FLOP CIRCUIT AND SYNCHRONOUS TYPE SEMICONDUCTOR MEMORY DEVICE CONTAINING IT 失效
公开(公告)号：JPH08106786A
公开(公告)日：1996-04-23
申请号：JP10642695
申请日：1995-04-28
申请人： MOSAID TECHNOLOGIES INC
发明人： BURUUSU MIRAA , RICHIYAADO SHII FUOSU , TOMASU UOISHIKUKI
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C11/4096
摘要： PURPOSE: To reduce the power consumption by providing a capture latch circuit for temporarily storing bits, and a unit for supplying data pulse from data input to the latch. CONSTITUTION: A body conductor memory stores the bits corresponding to data pulse in a capture latch 21 while the leading edge of a clock pulse coincides with the data pulse of one polarity, is enabled to strongly drive the pair of complementary outputs, the latch 21 is recharged and disabled continued to the leading edge of the clock pulse and the one polarity of the data pulse, and hence the strong drive for the complementary output as remained driven is removed.

53. 发明专利

JPH0845270A DRAM-PAGE COPYING METHOD 失效
公开(公告)号：JPH0845270A
公开(公告)日：1996-02-16
申请号：JP8377595
申请日：1995-04-10
申请人： MOSAID TECHNOLOGIES INC
发明人： PIITAA BII GIRINGAMU , RANDEII TOORENSU
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409
摘要： PURPOSE: To increase the data transfer rate of DRAM, especially the data copy rate between pages, by transferring bit signals from first group to second croup of memory cell in a DRAM while addressing the second group. CONSTITUTION: A bit line is charged with a predetermined voltage between supply voltages VCC and VSS during a predetermined precharge interval. A first word line (i) 4 is addressed during a first interval starting after a precharge interval. Consequently, the data in all memory cells connected with the line (i) 4 is transferred immediately to a bit line 4 and attenuated during next interval as a result of charge division between the capacities of cell and bit line. Subsequently, a sense amplifier is activated and the logic level of bit of a capacitor in memory cell appearing on the lead of bit line is sensed and amplified. Upon completion of sensing, the bit line is precharged again. Finally, word lines j, j+1 are addressed and a bit data is transferred to cells associated with the word lines j, j+1.

54. 发明专利

JP2013251045A Multiple independent serial link memory 审中-公开
标题翻译：多个独立的串行链路存储器
公开(公告)号：JP2013251045A
公开(公告)日：2013-12-12
申请号：JP2013158682
申请日：2013-07-31
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI , PYEON HONG BEOM
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： PROBLEM TO BE SOLVED: To provide an apparatus, system and method for controlling data transfer between serial data link interfaces and memory banks in a semiconductor memory.SOLUTION: In one example, a flash memory device with a plurality of serial data links and a plurality of memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between the memory devices. In addition, a virtual multiple link configuration is described where a single link is used to emulate multiple links.
摘要翻译：要解决的问题：提供一种用于控制半导体存储器中的串行数据链路接口和存储体之间的数据传输的装置，系统和方法。解决方案：在一个示例中，具有多个串行数据链路和多个的记忆库，其中链接独立于银行。闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。另外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

55. 发明专利

JP2013239234A Flash memory program inhibit scheme 有权
标题翻译：闪存存储器程序禁止方案
公开(公告)号：JP2013239234A
公开(公告)日：2013-11-28
申请号：JP2013182871
申请日：2013-09-04
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To minimize program disturb in flash memories.SOLUTION: To reduce program disturb in a NAND Flash memory cell string where no programming from an erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, a selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows a channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when a corresponding wordline is raised to a programming voltage. Because of the high boosting efficiency, pass voltage applied to gates of the remaining memory cells in the NAND string can be reduced compared to the prior art, thereby minimizing program disturb while allowing random page programming.
摘要翻译：要解决的问题：最小化闪存中的程序干扰。解决方案：为了减少不需要擦除状态编程的NAND闪存单元串中的程序干扰，使用局部增强通道禁止方案。在本地提升通道禁止方案中，在NAND串中未选择编程的选择的存储单元与NAND串中的其它单元解耦。这允许去耦合单元的通道在相应的字线升高到编程电压时被局部提升到足以抑制F-N通道的电压电平。由于高的提升效率，与现有技术相比，可以减少施加到NAND串中剩余存储单元的栅极的通过电压，从而使程序干扰最小化同时允许随机页面编程。

56. 发明专利

JP2013236398A Methods for clock signal synchronization in configuration of semiconductor devices connected in series 有权
标题翻译：串联连接的半导体器件的时钟信号同步方法
公开(公告)号：JP2013236398A
公开(公告)日：2013-11-21
申请号：JP2013155351
申请日：2013-07-26
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： OH HAK JUNE
IPC分类号： H04L7/02 , H03K5/00 , H04L7/00
CPC分类号： G11C19/00 , G06F1/10 , H03L7/0812
摘要： PROBLEM TO BE SOLVED: To provide methods and apparatus for synchronizing a clock signal propagated along a series connection configuration of semiconductor devices.SOLUTION: A system includes semiconductor devices connected in series and a system controller. Such a device receives a clock signal originating from a previous device, and provides a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal.
摘要翻译：要解决的问题：提供用于使沿着半导体器件的串联连接配置传播的时钟信号同步的方法和装置。解决方案：系统包括串联连接的半导体器件和系统控制器。这种设备接收来自先前设备的时钟信号，并且提供去往后续设备的同步时钟信号。该装置还包括时钟同步器，用于通过处理所接收的时钟信号和较早版本的同步时钟信号来产生同步时钟信号。所述设备还包括设备控制器，用于在处理所述同步时钟信号的早期版本时调整由所述时钟同步器使用的参数。

57. 发明专利

JP2013229100A Non-volatile memory with dynamic multi-mode operation 审中-公开
标题翻译：具有动态多模式操作的非易失性存储器
公开(公告)号：JP2013229100A
公开(公告)日：2013-11-07
申请号：JP2013160457
申请日：2013-08-01
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI
IPC分类号： G11C16/02 , G06F12/16 , G11C16/04
CPC分类号： G11C16/06 , G06F12/0246 , G06F2212/7204 , G06F2212/7206 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/349 , G11C16/3495 , G11C2211/5641 , G11C2211/5646
摘要： PROBLEM TO BE SOLVED: To provide a method and system for extending the life span of a flash memory device.SOLUTION: The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in a corresponding subdivision, where the subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize the lifespan of any subdivision of the multi-mode flash memory device.
摘要翻译：要解决的问题：提供一种延长闪存设备寿命的方法和系统。解决方案：闪存设备是动态配置的，可以将数据存储在每个单元（SBC）存储模式的单个位或多个位单元（MBC）模式，使得两个SBC数据和MBC数据在同一存储器阵列中共存。存储在每个存储器页面中的一个或多个标签位用于指示用于将数据存储在相应细分中的存储模式的类型，其中细分可以是存储体，块或页面。控制器监视对应于每个页面的编程擦除周期的数量，以选择性地改变存储模式，以便最大化多模式闪存设备的任何细分的寿命。

58. 发明专利

JP2013229045A Apparatus and method for capturing serial input data 有权
标题翻译：用于捕获串行输入数据的装置和方法
公开(公告)号：JP2013229045A
公开(公告)日：2013-11-07
申请号：JP2013131759
申请日：2013-06-24
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： PYEON HONG BEOM , OH HAK JUNE
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G11C5/066 , G06F13/1673 , G06F13/28 , G11C7/10 , G11C7/1078 , G11C7/1093 , G11C2207/107
摘要： PROBLEM TO BE SOLVED: To provide a serial input data processing apparatus which provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency.SOLUTION: Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register an address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of the multiple clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.
摘要翻译：要解决的问题：提供一种串行输入数据处理装置，其提供如何在不损失单个位的情况下捕获串行数据，同时在命令解码器中以高频执行命令解释。解决方案：预先的串行位的单个字节定义的序列被锁存，并且使用多个时钟临时存储位流。在将字节信息传送到分配的地址寄存器之前进行临时存储以注册地址。通过在多个时钟的前沿锁存串行输入的所有位流来执行地址注册和数据注册。在高频操作（例如，1GHz或1ns周期时间）期间，在命令解释期间，在命令比特流解释和下一比特数据流之间具有足够的时间余量，不需要额外的寄存器来存储比特数据。

59. 发明专利

JP2013218737A Apparatus and method of page program operation for memory devices with mirror back-up of data 有权
标题翻译：用于具有镜像备份数据的存储器件的页面程序操作的装置和方法
公开(公告)号：JP2013218737A
公开(公告)日：2013-10-24
申请号：JP2013157522
申请日：2013-07-30
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： PYEON HONG BEOM , KIM JIN-KI , OH HAK JUNE
IPC分类号： G06F12/16
CPC分类号： G06F13/4243 , G06F13/4247
摘要： PROBLEM TO BE SOLVED: To provide an apparatus and a method of page program operation.SOLUTION: When performing page program operation with a selected memory device, a memory controller loads data into a page buffer of one selected memory device and also into a page buffer of another selected memory device to store a back-up copy of the data. When the data is not successfully programmed into memory cells of the one selected memory device, the memory controller recovers the data from the page buffer of the other memory device. Since the copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in data storage elements of the memory controller.
摘要翻译：要解决的问题：提供一种页面编程操作的装置和方法。解决方案：当使用选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个选择的存储器件的页面缓冲器中并且还加载到页面缓冲器的另一个选择的存储器设备来存储数据的备份副本。当数据未成功编程到所选存储器件的存储器单元中时，存储器控制器从另一个存储器件的页面缓冲器中恢复数据。由于数据的副本存储在另一存储器件的页缓冲器中，因此存储器控制器不需要将数据本地存储在存储器控制器的数据存储元件中。

60. 发明专利

JP2013179660A Integrated circuit having data retention circuitry with low leakage and method thereof 有权
标题翻译：具有低泄漏的数据保持电路的集成电路及其方法
公开(公告)号：JP2013179660A
公开(公告)日：2013-09-09
申请号：JP2013095072
申请日：2013-04-30
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： BARRY HOBERMAN , DANIEL HILLMAN , WILLIAM WALKER , CHARAHAN JOHN , MICHAEL ZAMPAGLIONE , COLE ANDREW
IPC分类号： H03K3/037 , H03K3/356 , H03K3/3562 , H03K17/10
CPC分类号： H03K19/0016
摘要： PROBLEM TO BE SOLVED: To provide a system and method for data retention circuitry with low leakage.SOLUTION: An integrated circuit comprises: a first circuit; and a sleep transistor circuit. The first circuit receives input signals and processes the input signals. The first circuit also retains data in a sleep state that has low leakage. The sleep transistor circuit is coupled to the first circuit and receives a sleep signal that has a negative voltage. The sleep circuit reduces power consumption of the first circuit in the sleep state to have low leakage on the basis of the sleep signal while retaining the data in the first circuit.
摘要翻译：要解决的问题：提供具有低泄漏的数据保持电路的系统和方法。解决方案：集成电路包括：第一电路; 和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于睡眠状态的第一电路的功耗，以便在保持第一电路中的数据的同时基于睡眠信号具有低泄漏。

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