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51. 发明授权

US10229749B2 Nonvolatile memory storage system 有权
公开(公告)号：US10229749B2
公开(公告)日：2019-03-12
申请号：US15475670
申请日：2017-03-31
申请人： Eun Chu Oh , Pilsang Yoon , Jun Jin Kong , Hong Rak Son , Dongsup Jin
发明人： Eun Chu Oh , Pilsang Yoon , Jun Jin Kong , Hong Rak Son , Dongsup Jin
IPC分类号： G11C29/50 , G11C16/04 , G11C16/26 , G11C16/10
摘要： A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.

52. 发明授权

US10013211B2 Storage devices including nonvolatile memory devices and access methods for nonvolatile memory devices 有权
公开(公告)号：US10013211B2
公开(公告)日：2018-07-03
申请号：US15605404
申请日：2017-05-25
申请人： Donghwan Lee , Junjin Kong , Seongnam Kwon , Seungkyung Ro , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Donggi Lee , Heewon Lee
发明人： Donghwan Lee , Junjin Kong , Seongnam Kwon , Seungkyung Ro , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Donggi Lee , Heewon Lee
IPC分类号： G11C7/00 , G06F3/06 , G06N99/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0619 , G06F3/0656 , G06F3/0679 , G06N20/00 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A storage device may include a nonvolatile memory device, a buffer memory, and a controller. The controller may perform first accesses on the nonvolatile memory device using the buffer memory, collect access result information and access environment information of the first accesses in the buffer memory, and generate an access classifier that predicts a result of a second access to the nonvolatile memory device by performing machine learning based on the access result information and the access environment information collected in the buffer memory.

53. 发明授权

US09904492B2 Method for operating non-volatile memory controller 有权
公开(公告)号：US09904492B2
公开(公告)日：2018-02-27
申请号：US15065915
申请日：2016-03-10
申请人： Chang-Kyu Seol , Jun-Jin Kong , Hye-Jeong So , Hong-Rak Son , Young-Geon Yoo , Dong-Whan Lee , Dong-Sup Jin
发明人： Chang-Kyu Seol , Jun-Jin Kong , Hye-Jeong So , Hong-Rak Son , Young-Geon Yoo , Dong-Whan Lee , Dong-Sup Jin
IPC分类号： G06F3/06 , G06F11/10 , G11C11/56 , G11C29/04
CPC分类号： G06F3/0679 , G06F3/0619 , G06F3/064 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C2029/0411
摘要： Provided are methods for operating a non-volatile memory controller. A method for operating a non-volatile memory controller includes dividing data provided from a host into first unit data and second unit data, encoding the first unit data into first codewords including n number of bits (n is an integer equal to or more than 1), encoding the second unit data into second codewords including n-w number of bits (w is an integer less than n and equal to or more than 1) corresponding to a bit having a value of 0 among the n number of bits of the first codewords, performing bit-to-state mapping on the first codewords and the second codewords using a predetermined bitmap, and programming the first codewords and the second codewords to a first page and a second page of a non-volatile memory, respectively.

54. 发明授权

US09864544B2 Methods of operating memory systems for sub-block erase operation 有权
公开(公告)号：US09864544B2
公开(公告)日：2018-01-09
申请号：US15001275
申请日：2016-01-20
申请人： Eun Chu Oh , Hong Rak Son , Jun Jin Kong , Seong Hyeog Choi
发明人： Eun Chu Oh , Hong Rak Son , Jun Jin Kong , Seong Hyeog Choi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/06
CPC分类号： G06F3/0652 , G06F3/0614 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F3/0679 , G06F3/0688
摘要： A method of operating a memory system including memory blocks, each including memory cells and divided into at least first and second sub-blocks. The method includes performing a program operation on memory cells connected to at least one word line of the first and second sub-blocks using a first program method of programming data having a first number of bits, performing an erase operation on the first sub-block, and detecting a state of distribution of threshold voltages of memory cells of the first and second sub-blocks, and determining whether a program operation is to be performed on memory cells connected to a second adjacent word line including at least one word line adjacent to the first sub-block, out of the memory cells of the second sub-block, by using a second program method of programming data having a second number of bits, based on the detecting.

55. 发明授权

US09495518B2 Method of reliably reading data stored in multi-level cell (MLC) non-volatile memory 有权
标题翻译：可靠地读取存储在多级单元（MLC）非易失性存储器中的数据的方法
公开(公告)号：US09495518B2
公开(公告)日：2016-11-15
申请号：US13407333
申请日：2012-02-28
申请人： Yong June Kim , Hong Rak Son , Jae Hong Kim , Sang Yong Yoon , Ki Jun Lee , Jung Soo Chung , Seong Hyeog Choi
发明人： Yong June Kim , Hong Rak Son , Jae Hong Kim , Sang Yong Yoon , Ki Jun Lee , Jung Soo Chung , Seong Hyeog Choi
IPC分类号： G06F12/00 , G06F21/00 , G06F12/14 , G11C11/00 , G11C11/56 , G11C16/26 , G11C16/34 , G06F11/10
CPC分类号： G06F21/00 , G06F11/1012 , G06F11/108 , G06F12/00 , G06F12/14 , G11C11/00 , G11C11/5642 , G11C16/26 , G11C16/3418
摘要： An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.
摘要翻译：一种用于从非易失性存储器读取的装置和方法，由此使用软判决数据来确定硬判决数据的可靠性。从非易失性存储器读取的硬判决数据被去随机化，并且从非易失性存储器读取的软判决数据不被去随机化。使用软判决数据，硬判决数据被解码。

56. 发明授权

US09437310B2 Method of operating a memory system having an erase control unit 有权
标题翻译：一种具有擦除控制单元的存储系统的操作方法
公开(公告)号：US09437310B2
公开(公告)日：2016-09-06
申请号：US14827930
申请日：2015-08-17
申请人： Eun Chu Oh , Hong Rak Son , Junjin Kong
发明人： Eun Chu Oh , Hong Rak Son , Junjin Kong
IPC分类号： G11C16/10 , G11C16/16 , G11C11/56 , G11C16/34 , G11C16/26
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/26 , G11C16/3468
摘要： A method of operating a memory system including a nonvolatile memory including a memory block, and a memory controller including an erase control unit, includes performing pre-reading a plurality of memory cells connected to a selected word line of the memory block, generating an off cell count based on the pre-reading result, by operation of the erase control unit, comparing the off cell count with a reference value to generate a comparison result, and changing an erase operation condition based on the comparison result, by operation of the nonvolatile memory, and erasing the memory block according to the changed erase operation condition.
摘要翻译：一种操作包括包括存储器块的非易失性存储器的存储器系统的方法和包括擦除控制单元的存储器控制器，包括执行预读取连接到所述存储器块的选定字线的多个存储器单元，产生关断基于预读取结果的单元计数，通过擦除控制单元的操作，将关闭单元计数与参考值进行比较以产生比较结果，以及通过非易失性存储器的操作来改变基于比较结果的擦除操作条件存储器，并根据改变的擦除操作条件擦除存储器块。

57. 发明申请

US20160210083A1 METHODS OF OPERATING MEMORY SYSTEMS FOR SUB-BLOCK ERASE OPERATION 有权
标题翻译：操作用于子块擦除操作的存储器系统的方法
公开(公告)号：US20160210083A1
公开(公告)日：2016-07-21
申请号：US15001275
申请日：2016-01-20
申请人： Eun Chu OH , Hong Rak SON , Jun Jin KONG , Seong Hyeog CHOI
发明人： Eun Chu OH , Hong Rak SON , Jun Jin KONG , Seong Hyeog CHOI
IPC分类号： G06F3/06
CPC分类号： G06F3/0652 , G06F3/0614 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F3/0679 , G06F3/0688
摘要： A method of operating a memory system including memory blocks, each including memory cells and divided into at least first and second sub-blocks. The method includes performing a program operation on memory cells connected to at least one word line of the first and second sub-blocks using a first program method of programming data having a first number of bits, performing an erase operation on the first sub-block, and detecting a state of distribution of threshold voltages of memory cells of the first and second sub-blocks, and determining whether a program operation is to be performed on memory cells connected to a second adjacent word line including at least one word line adjacent to the first sub-block, out of the memory cells of the second sub-block, by using a second program method of programming data having a second number of bits, based on the detecting.
摘要翻译：一种操作包括存储器块的存储器系统的方法，每个存储器块包括存储器单元并被分成至少第一和第二子块。该方法包括使用编程具有第一位数的数据的第一编程方法对连接到第一和第二子块的至少一个字线的存储器单元执行编程操作，对第一子块执行擦除操作并且检测第一和第二子块的存储器单元的阈值电压的分布状态，并且确定是否对连接到第二相邻字线的存储器单元执行编程操作，该第二相邻字线包括与...相邻的至少一个字线基于检测，通过使用具有第二位数的数据的第二编程方法，在第二子块的存储单元之外的第一子块。

58. 发明申请

US20150332778A1 SEMICONDUCTOR MEMORY SYSTEMS USING REGRESSION ANALYSIS AND READ METHODS THEREOF 审中-公开
标题翻译：使用回归分析的半导体存储器系统及其读取方法
公开(公告)号：US20150332778A1
公开(公告)日：2015-11-19
申请号：US14811222
申请日：2015-07-28
申请人： Kwanghoon KIM , Junjin KONG , Changkyu SEOL , Hong Rak SON
发明人： Kwanghoon KIM , Junjin KONG , Changkyu SEOL , Hong Rak SON
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3422 , G11C16/349
摘要： A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.
摘要翻译：存储器系统包括：位计数器和回归分析器。位计数器被配置为基于使用多个不同的读取电压从所选择的存储器单元读取的数据生成多个计数值，多个计数值中的每一个表示具有阈值电压的存储器件的存储单元的数量在多个不同读取电压的对之间。回归分析器被配置为使用回归分析来基于多个计数值来确定所选择的存储器单元的读取电压。

59. 发明授权

US09158500B2 Device and method for processing data including generating a pseudo random number sequence 有权
标题翻译：用于处理数据的装置和方法，包括产生伪随机数序列
公开(公告)号：US09158500B2
公开(公告)日：2015-10-13
申请号：US13537297
申请日：2012-06-29
申请人： Ki Jun Lee , Jun Jin Kong , Yong June Kim , Jae Hong Kim , Hong Rak Son , Jung Soo Chung , Seong Hyeong Choi
发明人： Ki Jun Lee , Jun Jin Kong , Yong June Kim , Jae Hong Kim , Hong Rak Son , Jung Soo Chung , Seong Hyeong Choi
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583
摘要： A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.
摘要翻译：一种数据处理装置，包括转换电路和包括多个移位寄存器的串联连接的伪随机数发生器。转换电路从除串行连接的最后一个移位寄存器之外的多个移位寄存器中的一个的输出接收伪随机数序列，并且使用接收到的伪随机数序列将第一数据转换为第二数据。

60. 发明授权

US09093145B2 Non-volatile random access memory device and data read method thereof 有权
标题翻译：非易失性随机存取存储器件及其数据读取方法
公开(公告)号：US09093145B2
公开(公告)日：2015-07-28
申请号：US14141609
申请日：2013-12-27
申请人： Eun Chu Oh , JunJin Kong , Hong Rak Son , Younggeon Yoo
发明人： Eun Chu Oh , JunJin Kong , Hong Rak Son , Younggeon Yoo
IPC分类号： G11C7/00 , G11C13/00
CPC分类号： G11C13/004 , G11C11/16 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C2013/0054
摘要： A nonvolatile random access memory device includes a plurality of memory cells configured to store data therein, a plurality of reference cells separate from the memory cells, the reference cells each configured to output a corresponding reference cell signal, and a read/write circuit. The read/write circuit is configured to generate from the reference cell signals a reference signal which is variable to have a plurality of different reference levels. The read/write circuit is further configured to identify, in response to the reference signal, a logic state among a first logic state and a second logic state for each of one or more selected memory cells, and to output read data corresponding to the identified logic state.
摘要翻译：非易失性随机存取存储器件包括多个存储器单元，其被配置为在其中存储数据，多个参考单元与存储器单元分离，每个参考单元被配置为输出相应的参考单元信号，以及读/写电路。读/写电路被配置为从参考单元信号产生可变为具有多个不同参考电平的参考信号。读/写电路还被配置为响应于参考信号识别一个或多个所选择的存储器单元中的每一个的第一逻辑状态和第二逻辑状态之间的逻辑状态，并且输出与所识别的对应的读取数据逻辑状态。

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