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51. 发明授权

US07939908B2 High-voltage transistor having shielding gate 有权
标题翻译：具有屏蔽门的高电压晶体管
公开(公告)号：US07939908B2
公开(公告)日：2011-05-10
申请号：US11510584
申请日：2006-08-28
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L21/76
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译：半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。

52. 发明申请

US20110062509A1 SEMICONDUCTOR DEVICE HAVING UPPER LAYER PORTION OF SEMICONDUCTOR SUBSTRATE DIVIDED INTO A PLURALITY OF ACTIVE AREAS 有权
标题翻译：具有分布在多个活跃区域中的半导体衬底的上层部分的半导体器件
公开(公告)号：US20110062509A1
公开(公告)日：2011-03-17
申请号：US12725848
申请日：2010-03-17
申请人： Yoshiko KATO , Mitsuhiro Noguchi , Hiroyuki Kutsukake
发明人： Yoshiko KATO , Mitsuhiro Noguchi , Hiroyuki Kutsukake
IPC分类号： H01L29/792 , H01L29/78
CPC分类号： H01L27/11529 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L29/1083 , H01L29/66825
摘要： A semiconductor memory device includes: a semiconductor substrate; a plurality of element isolation insulators disposed in parts of an upper layer portion of the semiconductor substrate and dividing the upper layer portion into a plurality of active areas extended in one direction; tunnel insulating films provided on the active areas: charge storage members provided on the tunnel insulating films; and control gate electrodes provided on the charge storage members. A width of a middle portion of one of the active areas in the up-to-down direction being smaller than a width of a portion of the active areas upper of the middle portion and a width of a portion of the active areas below the middle portion.
摘要翻译：半导体存储器件包括：半导体衬底; 多个元件隔离绝缘体，设置在所述半导体衬底的上层部分的一部分中，并将所述上层部分分成沿一个方向延伸的多个有效区域; 设置在有源区域上的隧道绝缘膜：设置在隧道绝缘膜上的电荷存储构件; 以及设置在电荷存储部件上的控制栅电极。一个有源区域的上下方向的中间部分的宽度小于中间部分的有效区域的一部分的宽度，以及在中间部分之下的有效区域的一部分的宽度一部分。

53. 发明申请

US20100124117A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20100124117A1
公开(公告)日：2010-05-20
申请号：US12618200
申请日：2009-11-13
申请人： Hiroyuki KUTSUKAKE , Kenji GOMIKAWA , Mitsuhiro NOGUCHI , Kikuko SUGIMAE , Masato Endo , Takuya FUTATSUYAMA , Koji KATO , Kanae UCHIDA
发明人： Hiroyuki KUTSUKAKE , Kenji GOMIKAWA , Mitsuhiro NOGUCHI , Kikuko SUGIMAE , Masato Endo , Takuya FUTATSUYAMA , Koji KATO , Kanae UCHIDA
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/16 , H01L27/11521 , H01L27/11526
摘要： A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.
摘要翻译：存储器包括连接到第一存储单元的控制栅电极的第一字线，连接到第二存储单元的控制栅极的第二字线，连接到第二存储单元的控制栅电极的电位传输线第一和第二字线，连接在第一字线和电位传输线之间的第一N沟道MOS晶体管和连接在第二字线和电位传输线之间的第二N沟道MOS晶体管。控制电路向半导体衬底提供具有正值的第一电位，并向电位传输线提供具有低于第一电位的正值的第二电位，以使第一N沟道MOS晶体管导通，并转向第二N沟道MOS晶体管截止，以擦除第一存储单元的数据。

54. 发明申请

US20100044769A1 METHOD OF MANUFACTURE OF CONTACT PLUG AND INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE 有权
标题翻译：触点插头和半导体器件互连层的制造方法
公开(公告)号：US20100044769A1
公开(公告)日：2010-02-25
申请号：US12610022
申请日：2009-10-30
申请人： Hiroyuki KUTSUKAKE , Yasuhiko MATSUNAGA , Shoichi MIYAZAKI
发明人： Hiroyuki KUTSUKAKE , Yasuhiko MATSUNAGA , Shoichi MIYAZAKI
IPC分类号： H01L29/78
CPC分类号： H01L23/485 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底的第一表面上沿着第一方向形成两个第一栅电极和在每个第一栅电极下夹着沟道区的源/漏区，形成第一层间绝缘层以填充在所述第一栅电极之间的区域中，降低所述第一层间绝缘层的顶部，在所述第一层间绝缘层上沉积第二层间绝缘层和所述第一栅电极，使所述第二层间绝缘层的表面平坦化，以及形成互连层和第一层间绝缘层和第二层间绝缘层中的接触塞，使得接触插塞与互连层和源极/漏极区之一接触。

55. 发明申请

US20090161427A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20090161427A1
公开(公告)日：2009-06-25
申请号：US12337808
申请日：2008-12-18
申请人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
发明人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/24
摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.
摘要翻译：非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

56. 发明授权

US07504294B2 Method of manufacturing an electrically erasable programmable read-only memory (EEPROM) 有权
标题翻译：制造电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US07504294B2
公开(公告)日：2009-03-17
申请号：US10881180
申请日：2004-07-01
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

57. 发明授权

US07417281B2 Semiconductor device with a selection gate and a peripheral gate 有权
标题翻译：具有选择栅极和外围栅极的半导体器件
公开(公告)号：US07417281B2
公开(公告)日：2008-08-26
申请号：US11733488
申请日：2007-04-10
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L29/94
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

58. 发明申请

US20080055992A1 SEMICONDUCTOR DEVICE WITH THE HIGH-BREAKDOWN-VOLTAGE TRANSISTORS 失效
标题翻译：具有高电压转换晶体管的半导体器件
公开(公告)号：US20080055992A1
公开(公告)日：2008-03-06
申请号：US11849707
申请日：2007-09-04
申请人： Hiroyuki Kutsukake , Kikuko Ishida
发明人： Hiroyuki Kutsukake , Kikuko Ishida
IPC分类号： G11C11/34
CPC分类号： G11C16/0483
摘要： A semiconductor device includes a unit high-breakdown-voltage transistor includes first to fourth high-breakdown-voltage transistors. The first high-breakdown-voltage transistor is connected to a first write line at the other end of the current path thereof, and includes a first gate which is disposed in a first direction. The second high-breakdown-voltage transistor is connected to a second write line at the other end of the current path thereof, and includes a second gate which is disposed in a second direction crossing the first direction. The third high-breakdown-voltage transistor is connected to a third write line at the other end of the current path thereof, and includes a third gate which is disposed in the first direction. The fourth high-breakdown-voltage transistor is connected to a fourth write line at the other end of the current path thereof, and includes a fourth gate which is disposed in the second direction.
摘要翻译：半导体器件包括单元高击穿电压晶体管，其包括第一至第四高击穿电压晶体管。第一高击穿电压晶体管在其电流路径的另一端连接到第一写入线，并且包括设置在第一方向上的第一栅极。第二高击穿电压晶体管在其电流路径的另一端连接到第二写入线，并且包括沿与第一方向交叉的第二方向设置的第二栅极。第三高击穿电压晶体管在其电流通路的另一端连接到第三写入线，并且包括沿第一方向设置的第三栅极。第四高击穿电压晶体管在其电流通路的另一端连接到第四写入线，并且包括沿第二方向设置的第四栅极。

59. 发明申请

US20060202257A1 Nonvolatile semiconductor memory device 失效
公开(公告)号：US20060202257A1
公开(公告)日：2006-09-14
申请号：US11430170
申请日：2006-05-09
申请人： Hiroyuki Kutsukake , Kikuko Sugimae
发明人： Hiroyuki Kutsukake , Kikuko Sugimae
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/764 , H01L27/115 , H01L27/11519 , H01L27/11524
摘要： A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate formed on the substrate via a second gate insulation film, and a pair of second diffusion layers formed in the substrate positioned on the opposite sides of the selection gate and one of which is electrically connected to one of the pair of first diffusion layers.

60. 发明申请

US20060197160A1 Nonvolatile semiconductor memory device 审中-公开
公开(公告)号：US20060197160A1
公开(公告)日：2006-09-07
申请号：US11429311
申请日：2006-05-08
申请人： Kikuko Sugimae , Hiroyuki Kutsukake
发明人： Kikuko Sugimae , Hiroyuki Kutsukake
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate•wiring including a first portion constituted of the same conductive layer as the first conductive layer, and a second portion constituted of the same conductive layer as the second conductive layer, and a second diffusion layer formed in the substrate, facing the second portion of the selection gate•wiring.

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