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51. 发明申请

US20140021523A1 DRAM WITH DUAL LEVEL WORD LINES 有权
公开(公告)号：US20140021523A1
公开(公告)日：2014-01-23
申请号：US13551766
申请日：2012-07-18
申请人： Babar A. Khan , Effendi Leobandung
发明人： Babar A. Khan , Effendi Leobandung
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10867 , H01L21/84 , H01L27/0207 , H01L27/10891 , H01L27/1203 , H01L29/945
摘要： A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

52. 发明申请

US20140015054A1 FIELD EFFECT TRANSISTOR DEVICES HAVING THICK GATE DIELECTRIC LAYERS AND THIN GATE DIELECTRIC LAYERS 审中-公开
标题翻译：具有厚栅介质层和薄栅介质层的场效应晶体管器件
公开(公告)号：US20140015054A1
公开(公告)日：2014-01-16
申请号：US13552936
申请日：2012-07-19
申请人： Effendi Leobandung , Junli Wang
发明人： Effendi Leobandung , Junli Wang
IPC分类号： H01L27/12 , H01L27/092
CPC分类号： H01L21/823431 , H01L21/823443 , H01L21/823456 , H01L21/823462 , H01L29/66545
摘要： A semiconductor device includes a substrate, a fin arranged on the substrate, a first field effect transistor (FET) comprising a first gate stack disposed over the a portion of the fin, the first gate stack including a polysilicon layer and a silicide material disposed on the polysilicon layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the first FET, and a second effect transistor (FET) comprising a second gate stack disposed over the a portion of the fin, the second gate stack including a metal gate material layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the second FET.
摘要翻译：半导体器件包括衬底，布置在衬底上的鳍片，第一场效应晶体管（FET），包括设置在鳍片的一部分上的第一栅极堆叠，第一栅极堆叠包括多晶硅层和硅化物材料所述多晶硅层和设置在所述鳍的部分上的外延材料，所述外延材料限定所述第一FET的源极和漏极区，以及第二效应晶体管（FET），所述第二效应晶体管包括设置在所述鳍的一部分上方的第二栅极堆叠，所述第二栅极堆叠包括金属栅极材料层和设置在所述鳍的一部分上的外延材料，所述外延材料限定所述第二FET的源极和漏极区。

53. 发明申请

US20130316513A1 FIN ISOLATION FOR MULTIGATE TRANSISTORS 审中-公开
标题翻译： FIN分离多晶硅晶体管
公开(公告)号：US20130316513A1
公开(公告)日：2013-11-28
申请号：US13478976
申请日：2012-05-23
申请人： VEERARAGHAVAN S. BASKER , EFFENDI LEOBANDUNG , TENKO YAMASHITA , CHUN-CHEN YEH
发明人： VEERARAGHAVAN S. BASKER , EFFENDI LEOBANDUNG , TENKO YAMASHITA , CHUN-CHEN YEH
IPC分类号： H01L21/762
CPC分类号： H01L21/845 , H01L27/1211
摘要： Multigate transistor devices and methods of their fabrication are disclosed. In one method, a substrate including a semiconductor upper layer and a lower layer beneath the upper layer is provided. The lower layer has a rate of transformation into a dielectric that is higher than a rate of transformation into a dielectric of the upper layer when the upper and lower layers are subjected to dielectric transformation conditions. Fins are formed in the upper layer, and the lower layer beneath the fins is transformed into a dielectric material to electrically isolate the fins. In addition, a gate structure is formed over the fins to complete the multigate transistor device.
摘要翻译：公开了多晶体管器件及其制造方法。在一种方法中，提供了包括上层下面的半导体上层和下层的衬底。当上层和下层经历介电转变条件时，下层具有比电介质的转变速率高于上层电介质的转变速率。翅片形成在上层中，翅片下方的下层转变成电介质材料以电隔离翅片。此外，在鳍片之上形成栅极结构以完成多栅极晶体管器件。

54. 发明授权

US08557657B1 Retrograde substrate for deep trench capacitors 有权
标题翻译：深沟槽电容器逆行衬底
公开(公告)号：US08557657B1
公开(公告)日：2013-10-15
申请号：US13475485
申请日：2012-05-18
申请人： Veeraraghavan S. Basker , Wilfried E. Haensch , Effendi Leobandung , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Wilfried E. Haensch , Effendi Leobandung , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/108 , H01L29/00 , H01L31/036 , H01L31/112 , H01L21/8242 , H01L21/00
CPC分类号： H01L27/0629 , H01L21/84 , H01L21/845 , H01L27/0248 , H01L27/0255 , H01L27/10826 , H01L27/1087 , H01L27/10879 , H01L27/10894 , H01L27/1203 , H01L27/1211 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L31/112
摘要： A semiconductor device includes a substrate having a first doped portion to a first depth and a second doped portion below the first depth. A deep trench capacitor is formed in the substrate and extends below the first depth. The deep trench capacitor has a buried plate that includes a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion.
摘要翻译：半导体器件包括具有第一深度的第一掺杂部分和低于第一深度的第二掺杂部分的衬底。深沟槽电容器形成在衬底中并在第一深度之下延伸。深沟槽电容器具有掩埋板，该掩埋板包括与衬底的第二掺杂部分形成导电连接并与第一掺杂部分电绝缘的掺杂剂类型。

55. 发明授权

US08492228B1 Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers 失效
标题翻译：场效应晶体管器件具有厚的栅极电介质层和薄的栅极电介质层
公开(公告)号：US08492228B1
公开(公告)日：2013-07-23
申请号：US13547647
申请日：2012-07-12
申请人： Effendi Leobandung , Junli Wang
发明人： Effendi Leobandung , Junli Wang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823431 , H01L21/823443 , H01L21/823456 , H01L21/823462 , H01L29/66545
摘要： A method includes forming a first gate stack over a portion of a fin, forming a dummy gate stack over the fin, growing an epitaxial material from exposed portions of the fin, forming a layer of dielectric material over the epitaxial material, the first gate stack, and the dummy gate stack, performing a planarizing process that removes portions of the layer of dielectric material, the first gate stack, and the dummy gate stack, pattering a first mask over portions of the layer of dielectric material and the dummy gate stack, forming a silicide material on exposed portions of the first gate stack, removing the first mask, pattering a second mask over portions of the layer of dielectric material and the first gate stack, removing a polysilicon portion of the dummy gate stack to define a cavity, removing the second mask, and forming a second gate stack in the cavity.
摘要翻译：一种方法包括在鳍片的一部分上形成第一栅极叠层，在鳍片上形成虚拟栅极叠层，从鳍片的暴露部分生长外延材料，在外延材料上形成电介质材料层，第一栅极堆叠和虚拟栅极堆叠，执行去除电介质材料层，第一栅极堆叠和伪栅极堆叠的部分的平坦化工艺，在电介质材料层和伪栅极堆叠的部分上形成第一掩模，在所述第一栅极堆叠的暴露部分上形成硅化物材料，去除所述第一掩模，在所述介电材料层和所述第一栅极堆叠的部分上形成第二掩模，去除所述伪栅极堆叠的多晶硅部分以限定空腔，移除所述第二掩模，以及在所述空腔中形成第二栅极叠层。

56. 发明申请

US20130161744A1 FINFET WITH MERGED FINS AND VERTICAL SILICIDE 有权
标题翻译：具有合并的FINS和垂直硅胶的FINFET
公开(公告)号：US20130161744A1
公开(公告)日：2013-06-27
申请号：US13337874
申请日：2011-12-27
申请人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

57. 发明申请

US20130032929A1 METHOD OF PROTECTING DEEP TRENCH SIDEWALL FROM PROCESS DAMAGE 审中-公开
标题翻译：从过程损坏中保护深层钢板的方法
公开(公告)号：US20130032929A1
公开(公告)日：2013-02-07
申请号：US13198873
申请日：2011-08-05
申请人： Effendi Leobandung
发明人： Effendi Leobandung
IPC分类号： H01L23/482 , H01L21/311
CPC分类号： H01L27/1087 , H01L21/76224 , H01L21/84 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： Method of protecting a liner in a previously formed deep trench module from subsequent processing steps, and resulting structure. A deep trench module includes a deep trench with one or more liner films and a fill material in an SOI substrate. A mask layer is patterned to form first and second masks aligned over the liner films on first and second sidewalls of the deep trench, respectively. Further etching creates a polysilicon tab under the first mask which protects the liner film adjacent the first sidewall from being exposed during subsequent etches. The second mask protects its underlying polysilicon from subsequent etches to maintain a conduction strap from SOI layer to deep trench. The masks are removed. An isolation film is deposited on the substrate and planarized to form and isolation region. The resulting structure has a polysilicon tab interposed between the deep trench liner and the isolation region.
摘要翻译：在先前形成的深沟槽模块中保护衬垫的方法不受后续处理步骤的影响，以及结果。深沟槽模块包括具有一个或多个衬垫膜的深沟槽和SOI衬底中的填充材料。图案化掩模层以形成分别在深沟槽的第一和第二侧壁上的衬垫膜上对准的第一和第二掩模。进一步的蚀刻在第一掩模下形成多晶硅片，保护邻近第一侧壁的衬垫膜在随后的蚀刻期间被暴露。第二个掩模保护其底层多晶硅免受后续腐蚀，以保持从SOI层到深沟槽的导带。去除面具。将隔离膜沉积在衬底上并平坦化以形成和分离区域。所得结构具有插入深沟槽衬垫和隔离区之间的多晶硅片。

58. 发明授权

US08138497B2 Test structure for detecting via contact shorting in shallow trench isolation regions 有权
标题翻译：用于检测浅沟槽隔离区域中接触短路的测试结构
公开(公告)号：US08138497B2
公开(公告)日：2012-03-20
申请号：US12140479
申请日：2008-06-17
申请人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
发明人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
IPC分类号： H01L23/544
CPC分类号： H01L21/76227 , H01L21/823481 , H01L22/34
摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.
摘要翻译：用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

59. 发明申请

US20080246032A1 TEST STRUCTURE FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS 有权
标题翻译：用于通过SHOREOW TRENCH隔离区域中的接触短路检测的测试结构
公开(公告)号：US20080246032A1
公开(公告)日：2008-10-09
申请号：US12140479
申请日：2008-06-17
申请人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
发明人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
IPC分类号： H01L21/66
CPC分类号： H01L21/76227 , H01L21/823481 , H01L22/34
摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.
摘要翻译：用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

60. 发明授权

US07416986B2 Test structure and method for detecting via contact shorting in shallow trench isolation regions 有权
标题翻译：在浅沟槽隔离区域通过接触短路检测的测试结构和方法
公开(公告)号：US07416986B2
公开(公告)日：2008-08-26
申请号：US11469940
申请日：2006-09-05
申请人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
发明人： Huilong Zhu , Shih-Fen Huang , Effendi Leobandung
IPC分类号： H01L21/311
CPC分类号： H01L21/76227 , H01L21/823481 , H01L22/34
摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.
摘要翻译：用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

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